hi,
i am facing this problem mentioned below in the utilization summary..
i have made filter code in system generator then generate vhd for the
same.
when i am running this vhd code in ISE and synthesis, i am receiving
this warning..
how can i remove this warning?
Device utilization summary:
---------------------------
Selected Device : 5vlx110tff1136-1
Slice Logic Utilization:
Number of Slice LUTs: 7621 out of 69120 11%
Number used as Logic: 7621 out of 69120 11%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 7621
Number with an unused Flip Flop: 7621 out of 7621 100%
Number with an unused LUT: 0 out of 7621 0%
Number of fully used LUT-FF pairs: 0 out of 7621 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 9458
Number of bonded IOBs: 9458 out of 640 1477% (*)
Specific Feature Utilization:
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
:
> Number of bonded IOBs: 9458 out of 640 1477% (*)
probably you should connect your internal signals to something internal,
not to the output pins of your chip!
deepak singh wrote: > Number of bonded IOBs: 9458 out of 640 1477% (*) You want to connect nearly 10 thousand IO signals in the top level to the FPGA pins? It looks like you connected an array/ram/memory directly to the ports in the top level entity.
> how can i remove this warning?
Lothar pointed out the problem, but behind all there ist huge lack of
understanding in FPGA-Desing and Design-Flow.
I strongly recomend you to do some basic tutorial stuff. Unless you dont
understand what you are doing your results will be complete rubbish.
In order to understand your request we shall have a telecon. Please make yourself available. Please advice. Please confirm.
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