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Forum: FPGA, VHDL & Verilog FIFO in VHDL


Author: nick kolivas (Company: university) (tonionio)
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Hi there guys!

I want to build a router in order to use it as a generic component to 
build a mesh interconnections networks of 64 cores.
So to begin with I must build the one router.
I am planning in using the FIFO for input buffer an FSM to control the 
read and write a XY logic element for routing the same for the output 
only there I ll use an arbiter to arbitrate the request and a central 
crosspoint matrix.

Soto begin with I want to build the FIFO having inputs of :data in ,clk, 
write,read and outsof : the first4bits of the header are used for 
routing ,data out,fifo full, fifo empty.

Thank you in advance.

Author: PittyJ (Guest)
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Open Quartus II
Menu 'Tools' -> 'Megawizard Plugin Manager'
Select 'Memory Compilier' -> Fifo
Enter your parameters.


Or
Open ISE
'Tools' -> 'Core Generator'
'Memory & Storage Elements' -> Fifo
Enter your parameters.

Author: nick kolivas (Company: university) (tonionio)
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I am getting a message there is now project open!I have opened a new 
project but again I cannot load the fifo!

:( Is it because I have the free version of ISIM?

Author: nick kolivas (Company: university) (tonionio)
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Ok I have done it...But I dont really know how to set the right 
parameters before generating it :(

I need Data input ,clk,write and read , and outputs :first 4 bits of 
header for routing , dataout ,fifofull,fifoempty.

Can I implement these ports to have the requesting fifo?

Author: PittyJ (Guest)
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I think, you should sit down, take some books and Xilinx documents and 
read about the basics.

Look, what Xilinx offers you in their fifo-design. And then look, what 
signals you have to combine for your purpose.

Author: nick kolivas (Company: university) (tonionio)
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I think you are right and thats what I am doing...

Any suggestions on books or xilinx documents?

Author: P. K. (pek)
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Go to Google, enter "xilinx ise fifo generator" and take what you think 
fits best your needs.

Have a nice weekend... ;-)

Author: nick kolivas (Company: university) (tonionio)
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Could I please ask how can I testbench a core generator FIFO?
I mean I have done all the steps to generate the fifo with the i/o i 
need and I cannot understand what to do next  to tb it!

Will I have to write the tb?Is there a tb ready in the core to use?

cheers :)

Author: Duke Scarring (Guest)
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> Will I have to write the tb?
Yes, I think so.
Normally you have a global system, where the FIFO is only a small part.
I do normally a simulation of the global system...

> Is there a tb ready in the core to use?
I don't think so. FIFO is not MIG.

Duke

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