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Forum: FPGA, VHDL & Verilog VHDL code 3 bit multiplier using half adder and full adder and also and gate


Author: hor chin (vandread)
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i try to do the vhdl code for 3 bit multiplier but i getting confuse and 
confuse when try to create the code can someone help me??

Author: PittyJ (Guest)
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Let the VHDL compiler make it for you.

...

signal a:integer range 0 to 7:=5 ;
signal b:integer range 0 to 7:=6;

signal c:integer range 0 to 16 :=7;

signal result : integer range 0 to 127;
...

begin

  Timer: process (Clock_50MHz) is begin

    if rising_edge(Clock_50MHZ) then
       result <= a*b+c;
       a      <= a -1;
    end if;

  end process;
...

Author: hor chin (vandread)
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ehhh...dun understand....i using quartus 2 altera web edition, can it 
make something like this??

Author: PittyJ (Guest)
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Why do you not check it out? Enter your code and let quartus synthesize 
it!

Where ist the problem to test it out?

Author: Lothar Miller (lkmiller) (Moderator)
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hor chin wrote:
> can someone help me??
Show what you have and report whats the problem with it. Then someone 
might help you, but we intend not to do your homework completely...

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