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Forum: FPGA, VHDL & Verilog debug of a vhdl code for a digital integrator


Author: Pratyush Anand (pratyush23)
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I m trying to work on a digital integrator..i have the verilog code of 
the integrator as follows...

module dig_int(output reg y, input x,clock);
  reg z='b0;

  always @(x,z)
  y=x+z;

  always @(posedge clock)
  z<=y;

endmodule

i used x-hdl to convert it to a vhdl equivalent..and the code generated 
was as follows...


LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;


ENTITY dig_int IS
   PORT (
      y      : OUT STD_LOGIC;
      x      : IN STD_LOGIC;
      clock  : IN STD_LOGIC
   );
END dig_int;

ARCHITECTURE trans OF dig_int IS

   SIGNAL z       : STD_LOGIC := '0';
   SIGNAL y_xhdl0 : STD_LOGIC;

BEGIN

   y <= y_xhdl0;

   PROCESS (x, z)
   BEGIN
      y_xhdl0 <= x + z;
   END PROCESS;

   PROCESS (clock)
   BEGIN
      IF (clock'EVENT AND clock = '1') THEN
         z <= y_xhdl0;
      END IF;
   END PROCESS;


END trans;

on synthesis of the above vhdl code, there is an error in the line
y_xhd10 <= x + z;

please suggest as to how to rectify the above problem..or any other prb 
so that the code can be run error-free

thanks.

Author: Holger Bachwieser (Guest)
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you require to use std_log_vecor to use them as counters but it is a 
widely afreed fact that numeric should be your library when intending 
calculations

Author: Lothar Miller (lkmiller) (Moderator)
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Pratyush Anand wrote:

>  on synthesis of the above vhdl code, there is an error in the line
> y_xhd10 <= x + z;
Be more specific: what error?

> please suggest as to how to rectify the above problem..or any other prb
> so that the code can be run error-free
Your code is missing a library for std_logic arithmetics...

Or much better: use numeric_std for calculations.

Author: Pratyush Anand (pratyush23)
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Lothar Miller wrote:
> Pratyush Anand wrote:
>
>>  on synthesis of the above vhdl code, there is an error in the line
>> y_xhd10 <= x + z;
> Be more specific: what error?
>
>> please suggest as to how to rectify the above problem..or any other prb
>> so that the code can be run error-free
> Your code is missing a library for std_logic arithmetics...
>
> Or much better: use numeric_std for calculations.

the following error was reported...

ERROR:HDLParsers:808 - "E:/lgkfmg/kjnj.vhd" Line 49. + can not have such 
operands in this context.

i included the following libraries...

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_std.ALL;

...yet the problem persists...

Author: Pratyush Anand (pratyush23)
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Holger Bachwieser wrote:
> you require to use std_log_vecor to use them as counters but it is a
> widely afreed fact that numeric should be your library when intending
> calculations

the following error was reported...

ERROR:HDLParsers:808 - "E:/lgkfmg/kjnj.vhd" Line 49. + can not have such 
operands in this context.

i included the following libraries...

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_std.ALL;

...yet the problem persists...

Author: Lothar Miller (lkmiller) (Moderator)
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You cannot add two single bits together! What sense should that make? 
Instead you can:
1. understand what you want to do and simply EXOR those two bits
Or
2. Use single bit vectors  like this:
    SIGNAL z : STD_LOGIC_VECTOR( 0 DOWNTO 0);


And never ever use the std_logic_arith libs together with the 
numeric_std...

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