EmbDev.net

Forum: FPGA, VHDL & Verilog need verilog/vhdl programming help


Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
Hi all,
I need to design a decoder with the folling input and output:

input : AA0BB2CDFF1
output : AABBBBCDFFF

please help me if anyone has any idea of how to do this. Assume the 
input data are stored in BRAM. I am not getting any idea of reading 
consequtive data fromthe BRAM then compare the two data and depending on 
the comparison result next address is raed as count. please help...

: Locked by Admin
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
For future readers of this thread:
We come from http://embdev.net/topic/240164

> input : AA0BB2CDFF1
How do you distinguish between data and a lenght information?
"Numbers" and "Letters"?
A "Number" is repeat information, a "Letter" is data?

If Yes: do you know anything about hexadecimal values?
There 'A' is also a number as '9'...

> Assume the input data are stored in BRAM.
And where does it go after the computation? Do you just want to generate 
a serial stream? Or must the result be stored in a RAM afterwards?

Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
Thanks!

I am showing you the HEX file and its encoded format to make you 
understand my problem:

Decoded Data: AA 00 FF FF FF 00 00 00 AA AA FF FF FF FF FF
encoded Data : AA 00 FF FF 01 00 00 01 AA AA 00 FF FF 03

when ever two consequtive data bytes are same then the next byte will be 
read as the length of the bytes.



>And where does it go after the computation?
I want to to get serial stream of data  to the output. but input data 
should come from a BRAM.

please help!!

Author: Klaus Falser (kfalser)
Posted on:

Rate this post
0 useful
not useful
Why are you opening the same topic twice?

https://embdev.net/topic/240164#new

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

Rate this post
0 useful
not useful
> when ever two consequtive data bytes are same
> then the next byte will be read as the length of the bytes.
enc: AA AA 00 FF FF
dec: AA AA FF FF
This is a little bit tricky, because here you have to "skip" one 
cycle...

So, you can output Data with half the clock rate.
Or you can generate a "valid" signal parallel to the output data.
Or you can generate a clock signal that "clocks" out valid data (with 
half the clock rate).

Here a solution for the 3rd way:
-- decoded Data: AA 00 FF FF FF 00 00 00 AA AA FF FF FF FF FF
-- encoded Data: AA 00 FF FF 01 00 00 01 AA AA 00 FF FF 03
-- when ever two consequtive data bytes are same 
-- then the next byte will be read as the length of the bytes.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RLD is
    Port ( clk   : in  STD_LOGIC;
           cout  : out  STD_LOGIC;
           lastut  : out  STD_LOGIC_VECTOR(7 lastwnto 0));
end RLD;

architecture Behavioral of RLD is
   type RAM_t is array (0 to 15) of std_logic_vector (7 lastwnto 0); 
   signal RAM : RAM_t := ( x"AA", x"00", x"FF", x"FF", x"01", x"00", x"00", x"01", x"AA", x"AA", x"00", x"FF", x"FF", x"03", others=>x"00");
   signal idx : integer range RAM_t'range := 0;
   signal rpt : integer range 0 to 255;   -- repeat counter max. 255
   signal last : std_logic_vector(7 lastwnto 0) := x"FF"; -- for lastuble-byte check: beware the first byte in RAM being xff!
   signal gl : std_logic := '0'; -- get length out of RAM
   signal phase : std_logic := '0';
begin

   process begin
      wait until rising_edge(clk);
      phase <= not phase;
      if (phase='0') then
         if (rpt>0) then           -- something to repeat?
           rpt <= rpt-1;
         else
            idx <= idx+1;          -- beware of reaching the end of the RAM!
            if (last=RAM(idx)) then  -- next: get length
               gl <= '1'; 
            else 
               last <= RAM(idx);
            end if;
         end if;
      else
         if (gl='1') then          -- get length
            rpt <= to_integer(unsigned(RAM(idx)));
            idx <= idx+1;          -- beware of reaching the end of the RAM!
         end if;
         gl <= '0';
      end if;
   end process;

   lastut <= last;
   cout <= phase;
   
end Behavioral;

Result: see screenshot.

Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
Thanks a lot Lother Miller !

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

Rate this post
0 useful
not useful
> Thanks a lot Lother Miller !
De nada.
Just a little remark: replace the "lastwnto" with "downto". It was a 
search and replace lapse...  :-/


But my style would be the second one: generate a valid signal in 
parallel to the clock and the data.
-- decoded Data: AA 00 FF FF FF 00 00 00 AA AA FF FF FF FF FF
-- encoded Data: AA 00 FF FF 01 00 00 01 AA AA 00 FF FF 03
-- when ever two consequtive data bytes are same 
-- then the next byte will be read as the length of the bytes.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RLD is
    Port ( clk   : in  STD_LOGIC;
           cout  : out  STD_LOGIC;
           dout  : out  STD_LOGIC_VECTOR(7 downto 0));
end RLD;

architecture Behavioral of RLD is
   type RAM_t is array (0 to 15) of std_logic_vector (7 downto 0); 
   signal RAM : RAM_t := ( x"AA", x"00", x"FF", x"FF", x"01", x"00", x"00", x"01", x"AA", x"AA", x"00", x"FF", x"FF", x"03", others=>x"00");
   signal idx : integer range RAM_t'range := 0;
   signal rpt : integer range 0 to 255;   -- repeat counter max. 255
   signal last : std_logic_vector(7 downto 0) := x"FF"; -- for lastuble-byte check: beware the first byte in RAM being xff!
   signal valid : std_logic := '1';
begin

   process begin
      wait until rising_edge(clk);
      if (rpt>0) then      -- something to repeat?
        rpt <= rpt-1;
        valid <= '1';
      else
         idx <= idx+1;
         if (idx<15) then
            if (valid='0') then -- get length
               rpt   <= to_integer(unsigned(RAM(idx)));
               valid <= '1';
            else
               if (last=RAM(idx)) then -- next: get length
                  valid <= '0'; 
               else 
                  last <= RAM(idx);
               end if;
            end if;
         else
            valid <= '0';
         end if;
      end if;
   end process;

   dout <= last;
   cout <= valid;
--   cout <= valid and clk; -- just for debugging: one pulse per byte
end Behavioral;

In the screenshot you must look at the rising edges of the clock an the 
signal values before that. Those two belong togehter.

Author: pakhi new (manideepa) Flattr this
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hi Miller,
 I want to load data to the RAM from a file.I tried what you have 
suggested(google transtate the code) but the code is not working. please 
help me how to read the attached file and store data into the RAM to 
simulate the program you gave me. Please help!!

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

Rate this post
0 useful
not useful
> please help me how to read the attached file and store data into the RAM
> to simulate the program you gave me. Please help!!
Where does this file come from?
Is it a bit stream for a fpga (looks like), or what?
And what do you want with this bitstream in a RAM?

Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
Yes,
it is a compressed bitstream for FPGA. I have compressed this file to 
the adder1.bit, now I want to see the simulation result using the code u 
gave that it is giving out the same bitstream from which I have 
compressed.How can i do that?

Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
how can I load the file to simulate the program? please help

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> how can I load the file to simulate the program?
What you can simulate is a HDL description or a timing model of your 
fpga design. But you cannot simulate a bitstream file. Thats a file that 
must be loaded into a FPGA by a programming cable or something 
similar...

Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
Hi lother,
How can I know that what will be the no of clock cycle the decompressor 
is taking to decompress the data if my input data is large? is their any 
relation between the decoded/encoded data and the clock cycle?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> How can I know that what will be the no of clock cycle the decompressor
> is taking to decompress the data if my input data is large?
Even if the input data is "short" you cannot know the final length 
until its decompressed. But a calculation of the final length could be 
done with less clock cycles. Its just stepping through the ram and 
adding the bytes and the "repeat" values.

> is their any
> relation between the decoded/encoded data and the clock cycle?
I do not understand this question...  :-/
Its a synchronous design, and so for sure there is a relation to the 
clock. What other relation do you expect?

Author: pakhi new (manideepa) Flattr this
Posted on:

Rate this post
0 useful
not useful
Hi,

I got that answer for my previous question but I am stuck with another 
problem. is your code synthesizable ? it is giving a warnnin that Signal 
'RAM' is not connected in block 'RLD' ties to its initial value.
and when I am going to systhesize the code It is showing No 
combinational path delay. Is the code is not synthesizable?
In simulator there is an error coming:
ERROR: Index 16 out of bound 0 to 15.
ERROR: In process decoder.vhd:17

please help

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> is your code synthesizable ?
With Xilinx XST it is.

> and when I am going to systhesize the code It is showing No
> combinational path delay.
Do you know what a combinational path delay is?
There is no combinational path in that design, because there is no path 
between an input pin and an output pin.

> In simulator there is an error coming:
> ERROR: Index 16 out of bound 0 to 15.
Ahm....... as far as I see, that message is correct.
But why does it occur? Did you figure that out? Did you see the comment 
I wrote there:
   idx <= idx+1;     -- beware of reaching the end of the RAM!
Just do a little of work by yourself and (at least) try to 
understand what I did, then what you are doing, and then think about 
such comments and corresponding error messages.

Author: Andreas Schwarz (andreas) (Admin) Flattr this
Posted on:

Rate this post
0 useful
not useful
Lothar Miller wrote:
> Just do a little of work by yourself...

...or this thread will be closed. It is commendable that Lothar is 
putting so much effort into helping others, but I do not like that 
people think this is a place to get their homework done with no effort 
of their own.

This topic is locked and can not be replied to.