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Forum: FPGA, VHDL & Verilog RS FlipFlop in 22V10


Author: Dan Lee (Guest)
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I want output q0 to toggle each time the combinatorial equation becomes 
true. I am trying setup q0 as an RS FlipFlop, but continually get errors 
on compiling.

/* *************** INPUT PINS ******************** */
PIN  1  =       Cyl1_6                  ; /* 
*/
PIN  2  =       Cyl3_5                  ; /* 
*/
PIN  3  =       Cyl7_4                  ; /* 
*/
PIN  4  =       Cyl2_8                  ; /* 
*/
PIN  5  =       OS1_6                  ; /* 
*/
PIN  6  =       OS3_5                  ; /* 
*/
PIN  7  =       OS7_4                 ; /* 
*/
PIN  8  =       OS2_8                  ; /* 
*/
PIN  9  =       EN1                  ; /* 
*/
PIN  10 =   EN2      ;/*          */
PIN  11 =   NU1      ;/*          */
PIN  13 =   NU2      ;/*          */


/* *************** OUTPUT PINS ******************* */
PIN   23  =      CYL1                   ; /* 
*/
PIN   22  =      CYL3                  ; /* 
*/
PIN   21  =      CYL7                   ; /* 
*/
PIN   20  =      CYL2                   ; /* 
*/
PIN   19  =      CYL6                   ; /* 
*/
PIN   18  =      CYL5      ; /*          */
PIN   17  =      CYL4                   ; /* 
*/
PIN   16  =      CYL8                  ; /* 
*/
PIN   15  =      q0                 ; /* 
*/
PIN   14  =      NEN1         ;/*


/* ***************lOGIC ************************* */

CYL1 = !(EN1 & Cyl1_6)                  ; /* 
*/
CYL3 = !(EN1 & Cyl3_5)                  ; /* 
*/
CYL7 = !(EN1 & Cyl7_4)                  ; /* 
*/
CYL2 = !(EN1 & Cyl2_8)                  ; /* 
*/
CYL6 = !(EN2 & Cyl1_6)      ; /*                                 */
CYL5 = !(EN2 & Cyl3_5)      ; /*                                 */
CYL4 = !(EN2 & Cyl7_4)      ; /*                                 */
CYL8 = !(EN2 & Cyl2_8)      ; /*                                 */
NEN1 = !EN1        ; /*                                 */
q0.R = (!OS1_6 # !OS3_5 # !OS7_4 # !OS2_8) & q0  ;

q0.S = (!OS1_6 # !OS3_5 # !OS7_4 # !OS2_8) & !q0  ;

Author: Stefan Wimmer (wswbln)
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...I don't know which compiler you use and whether your syntax is OK, 
but you can always write RS flipflops in the style of

RSFF = (set condition) OR (RSFF AND NOT (reset condition))

Author: Dan Lee (Guest)
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Thanks,

I'll give it a try.

I think that I could achive the same results by configuring it as a 'D' 
type flip flop with !q fed back to the 'D' input. The flip flop can be 
clocked by the combiatorial expression becoming True.

Author: Stefan Wimmer (wswbln)
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Dan Lee wrote:
> I think that I could achive the same results by configuring it as a 'D'
> type flip flop with !q fed back to the 'D' input.

...which is exactly what I thought to suggest, but forgot to mention DFF 
and clock since I'm too used to synchronous designs :-)
I used Q (named 'RSFF') for the feedback.

> The flip flop can be clocked by the combiatorial expression
> becoming True.

a) I don't know if your PLD has combinatiorial terms (of sufficient size 
and speed) for the clock, but
b) combinatorial/gated clocks are always a bad idea.

Use a fast enough general clock and have the set/reset terms (and maybe 
clock enables) do the job!

Author: Dan Lee (Guest)
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The 22V10 uses Pin 1 for the clock input. I already have used Pin 1 for 
another variable input. I will have to rewire my breadboard to connect 
Pin 1 to the combinatorial output. Then use another output for the D 
Flipflop.

I'll take another crack at the RS FF.

Author: Dan Lee (Guest)
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The 22V10 does not support An RSFF. It will support Asychronous Reset 
and Synchronous Preset, but SP requires a clock. That gets me to the 
same point as with the D FF.

The DFF should work. I have to decide if I want to rewire the board. 
It's much easier to reprogram a device, than to rewire a board.

Author: Dan Lee (Guest)
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BTW, the combinatorial clock consists of 4 synchronous pulses or'ed to 
form a pulse train that represents the four quadrants of a rotating 
wheel. There should be no problem in the combining of these pulses into 
one pulse train.

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