EmbDev.net

Forum: FPGA, VHDL & Verilog error (10346)


Author: miri (Guest)
Posted on:

Rate this post
0 useful
not useful
This error on quartus: formal port or parameter "N" must have actual or 
default value

What does it mean?


Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;

entity shrBbits is
  generic (N:positive);
  port( A,B: in std_logic_vector(N-1 downto 0);
        OP: in std_logic_vector(2 downto 0);
        RES_LO:out std_logic_vector(N-1 downto 0)
    );
end entity;

Author: lkmiller (Guest)
Posted on:

Rate this post
0 useful
not useful
Write
(N:positive :=8)

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
I have this code:
Doing a shift to A - B times.

entity shrBbits is
  generic (N:positive:=32);
  port( A,B: in std_logic_vector(N-1 downto 0);
        OP: in std_logic_vector(2 downto 0);
        RES_LO:out std_logic_vector(N-1 downto 0)
    );
end entity;

architecture behv of shrBbits is
signal temp,temp_res: std_logic_vector(N-1 downto 0);
signal num:integer:=0;
begin
  process (A,B,OP,num,temp,temp_res)
  begin
  temp<=A;
  temp_res<=A;
  if (conv_integer(B)<0) then --for negative B
    num<=conv_integer(not (B))+1;
  else if num=0 then
      temp_res<=A;
      num<=conv_integer(B);
     else
      num<=conv_integer(B);
     end if;
  end if;
  temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE 
ERROR
  temp_res(num downto 0)<=temp(N-1 downto num);
  RES_LO<=temp_res;
  end process;
end behv;

How can it be changed?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
>-- HERE IS THE ERROR
WHAT error?
  temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE ERROR
No.
Your error happens much before!
How does a signal react in an process?
How does a variable react in a process?

However:
  temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE ERROR
Calculate this for N=32 and lets say num=3:
  temp_res(31 downto 4)     <=     temp(2 downto 0);
   this vector ^^^^  is MUCH longer than  ^^^^ this vector...  :-o

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
Yes - thanks - you right

it should be:
  temp_res(N-1 downto N-num)<= temp(num-1 downto 0);
  temp_res(N-num-1 downto 0)<=temp(N-1 downto num);


But it still gives me the same error.

Why?

Author: lkmiller (Guest)
Posted on:

Rate this post
0 useful
not useful
Assume num could become zero...

And beware: you will get latches for num also, because num is stored 
without a clock!

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
I have to do this task without clock?

It's strange to do it this way, but still, do you have some ideas to 
work it out?

thanks

Author: lkmiller (Guest)
Posted on:

Rate this post
0 useful
not useful
One question in advance:  can B become negative?

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
No. B is positive.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> No. B is positive.
So, why that:
  if (conv_integer(B)<0) then --for negative B

> Doing a shift to A - B times.
Really a shift?
A right shift or a left shift?
Or (as you do) a rotation?

With your name sh-r-B-bits I assume a right shift for B bits:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity shrBbits is
  generic (N:positive:=32);
  port( A,B: in std_logic_vector(N-1 downto 0);  -- why is B that big? 6 bits (0..32) would be enough!!!
        OP: in std_logic_vector(2 downto 0);     -- what is this OP good for?
        RES_LO:out std_logic_vector(N-1 downto 0)
    );
end entity;

architecture behv of shrBbits is
signal num  : integer range 0 to 2*N:=0;
signal hlp  : std_logic_vector(N*2-1 downto 0);
begin
   --  used ressources and delay times are for a Spartan 3 AN
   --  Number of Slices 75
   --  Maximum combinational path delay: 10.832ns
   process (A,B) 
   variable h : std_logic_vector(N-1 downto 0);
   variable c : integer range 0 to N:=0;
   begin
      h := A;
      c := to_integer(unsigned(B));
      for i in 0 to N-1 loop
         if i<c then
            h :=  '0' & h(N-1 downto 1);
         end if;
      end loop;
      RES_LO <= h;
   end process;
   
  -- Number of Slices 75
  -- Maximum combinational path delay: 10.912ns
  process (A,B) 
  variable h : std_logic_vector(N-1 downto 0);
  variable c : integer range 0 to N:=0;
  begin
     h := A;
     c := to_integer(unsigned(B));
     for i in 0 to N-1 loop
        if i=c then
           exit;
        end if;
        h := '0' & h(N-1 downto 1);
     end loop;
     RES_LO <= h;
  end process;

  -- Number of Slices 79
  -- Maximum combinational path delay: 11.445ns
  process (A,B) 
  variable h : std_logic_vector(N-1 downto 0);
  variable c : integer range 0 to N:=0;
  begin
     c := to_integer(unsigned(B));
     h := (others=>'0');
     h(N-1-c downto 0) := A(N-1 downto c);
     RES_LO <= h;
  end process;

  -- Number of Slices 82
  -- Maximum combinational path delay: 11.536ns
  num <= to_integer(unsigned(B));
  hlp <= x"00000000"&A;
  RES_LO <= hlp(N-1+num downto num);
 
end behv;
The last one can easily be changed to a rotate function:
   hlp <= A&A;

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

Rate this post
0 useful
not useful
I tested the code above with the attached stimuli "testbench".

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
For
 process (A,B)
  variable h : std_logic_vector(N-1 downto 0);
  variable c : integer range 0 to N:=0;
  begin
     c := to_integer(unsigned(B));
     h := (others=>'0');
     h(N-1-c downto 0) := A(N-1 downto c);
     RES_LO <= h;
  end process;

I still have an error "right bound of range must be constant".

What else might it be

Here is the full code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.pack.all;

-- this unit shift A bits number of B times to the right
-- if B is negative or zero the result is still A
-- the result is in res_shr
entity shrBbits is
  port( A: in std_logic_vector(N-1 downto 0);
        B: in std_logic_vector(N-1 downto 0);
        RES_SHR:out std_logic_vector(N-1 downto 0)
    );
end entity;

architecture behv of shrBbits is
begin
  process (A,B)
  variable h : std_logic_vector(N-1 downto 0);
  variable c : integer range 0 to N:=0;
  begin
     c := conv_integer(unsigned(B));
     h := (others=>'0');
     h(N-1-c downto 0) := A(N-1 downto c);
     RES_SHR <= h;
  end process;

end behv;

Thanks for the help,
Miri

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
I have this error while running Quartus

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> Here is the full code:
Lets say: except the missing definition of N...
I changed the code a little:
entity shrBbits is
  generic( N : integer := 16);
  port( .... );
end entity;

> I still have an error "right bound of range must be constant".
What toolchain?

EDIT: too late... :-/
> I have this error while running Quartus
With Xilinx XST this works fine...

BTW: you did see this in my code?
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Yes? Think about it...
A hint: the Synopsys libs are obsolete a long time ago and superseeded 
by the numeric_std.

BTW2: with
[ vhdl]
and
[ /vhdl]
(but without the blanks) and you can see a little magic:
and 

Author: miri pek (miripek)
Posted on:

Rate this post
0 useful
not useful
Quartus 64 bits.

tool chain - modelsim

Author: berndl (Guest)
Posted on:

Rate this post
0 useful
not useful
I'm not sure, but I think the problem with Quartus is:
h(N-1-c downto 0) := A(N-1 downto c);
ISE and Lattice Diamond can handle this, but Quartus may have a problem 
with this statement.

You could try to use a 'for i in 0 to N-1 loop' and assign just bitwise

Author: Amina Amin (Company: lebanon) (sweetamo)
Posted on:

Rate this post
0 useful
not useful
This error on quartus:Error (10346): VHDL error at accumu.vhd(18): 
formal port or parameter "m" must have actual or default value



What does it mean?


Here is my code:
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity acc is
port(x,y: in std_logic_vector(3 downto 0);
selacc,selpm,key: in std_logic;
somme: out std_logic_vector(3 downto 0));
end entity acc;

architecture structure of acc is
signal x0,x1,x2: std_logic_vector(3 downto 0);

begin
u0: mux2to1 port map(m0=>x,m1=>x1,mout=>x0, sel=>selacc);
u1 : adder4 port map(a=>y,b=>x0, sel=>selpm, cout=>open,z=>1);
u2:registre port map(clk=>key,d=>x1,q=>x2);


somme<=x2;
 end architecture structure ;



library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity adder4 is
port(m,n:in std_logic_vector(3 downto 0);
cin:in std_logic;
cout:out std_logic;
p:out std_logic_vector(3 downto 0));
end entity adder4;

architecture structure of adder4 is
signal c0,c1,c2:std_logic;
begin
fa0: fa port map(y=> m(0),x=> n(0),cin=>cin,s=>p(0),cout=>c0);
fa1: fa port map(y=> m(1),x=> n(1),cin=>cin,s=>p(1),cout=>c1);
fa2: fa port map(y=> m(2),x=> n(2),cin=>cin,s=>p(2),cout=>c2);
fa3: fa port map(y=> m(3),x=> n(3),cin=>cin,s=>p(3),cout=>cout);
end architecture structure;


library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
port(m0,m1:in std_logic_vector(3 downto 0);
mout:out std_logic_vector(3 downto 0);
sel:in std_logic);
end entity mux2to1;
architecture behavior of mux2to1 is
begin 
mout<=m0 when (sel='0')else m1;
end architecture behavior;


of course each i wrote each entity in a vhdl file

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Amina Amin wrote:
> Here is my code
Why do you not use some indetion to get a kind of readable code...

> of course each i wrote each entity in a vhdl file
You can have it in one file also, thats no problem. Or you could attach 
each of the files here, so it would be easier to find that line 18 in 
accumu.vhd...

However: what about simply using the same names for the port signals in 
the entity and in the port list?
u1 : adder4 port map(a=>y, b=>x0, sel=>selpm, cout=>open,z=>1); -- a,b,sel,cout and z

entity adder4 is
port(m,n:in std_logic_vector(3 downto 0); -- m,n,cin,cout and p
cin:in std_logic;
cout:out std_logic;
p:out std_logic_vector(3 downto 0));
end entity adder4;

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.