Hi. this is my vhdl code for a 4 bit counter using 1 half adder and 3
fulladders. i have done my code. bt the waveform only shows "0000" and
"0001". aftr "0001", it doesnt add anymore. how do i do that? Thanks in
advance!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter4 isport(count:outstd_logic_vector(3downto0);
clk:instd_logic;
reset:instd_logic);
end counter4;
architecture behav_counter4 of counter4 iscomponent ha port (a: instd_logic;
b: instd_logic;
sum: outstd_logic;
c_out: outstd_logic);
endcomponent;
component fa port (a, b, cin : instd_logic;
sum, c_out : outstd_logic);
endcomponent;
signal ain,s,c:std_logic_vector(3downto0) :="0000";
signal bin:std_logic_vector(3downto0):="0001";
--configuration specification forall:ha useentity work.ha(rtl);
forall:fa useentity work.fa(fa_behav);
begin
u1:ha portmap(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa portmap(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa portmap(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa portmap(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));
counter:process(clk, reset) --process(sensitivity list)beginif reset'event and (reset = '1') then
s <= (others => '0');
elsif clk'event and (clk='1') then
ain <= c xor ain;
s <= ain xor bin;
c <= s and c;
endif;
endprocess;
count <= s;
end behav_counter4;
This is not the complete description. I do not see anything about the
components ha and fa.
And as far as I see: if your ha and fa are working and the wiring is ok,
the only thing you must do in the process is this
counter:process(clk, reset) --process(sensitivity list)beginif (reset = '1') then
s <= (others => '0');
elsif (clk'event and clk='1') then
ain <= s;
endif;
endprocess;
And why?
Because the adder should do s=a+b.
With b=1 it does s=a+1.
And so for a counter you must just say a(new)=s(old) for each clock
cycle.
> if reset'event and (reset = '1') then
Whats that?
A clock sensitive reset? Thats not possible with real flipflops!
Another little problem:
Because the sum s is a result of a combinational calculation, its not
possible to reset it in a process.
But you can reset the counter flipflops. And these are the ain
flipflops, because they are affected by the clock. so it must look like
this:
counter:process(clk, reset) --process(sensitivity list)beginif (reset = '1') then
ain <= (others => '0');
elsif (clk'event and clk='1') then
ain <= s;
endif;
endprocess;
> begin
> if reset = '1'then
> s <= (others => '0');
> [...]
>
> Otherwise it will only react if there are events on reset signal...>> Duke
Now is shows 000X, 00XX and 0XXX only. its still not looping.
i used "if reset'event and (reset = '1') then
s <= (others => '0'); "
for my 8 bit counter and it worked.
> it still doesnt start frm 0000. it starts frm 0001.
Thats correct: ain is initialized as "0000".
And with s=ain+1 this results in "0000"+"0001"="0001"
So just try to initialize ain with "1111", because "1111"+"0001"="0000"
;-)
> signal ain :std_logic_vector(3 downto 0) :="1111";
Lothar Miller wrote:>> it still doesnt start frm 0000. it starts frm 0001.> Thats correct: ain is initialized as "0000".> And with s=ain+1 this results in "0000"+"0001"="0001"> So just try to initialize ain with "1111", because "1111"+"0001"="0000"> ;-)>> signal ain :std_logic_vector(3 downto 0) :="1111";
it still starts with 0001. and not 000o although ive changed the initial
values to 1111.
4bitcount.vhd:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter4 isport(count:outstd_logic_vector(3downto0);
clk:instd_logic;
reset:instd_logic);
end counter4;
architecture behav_counter4 of counter4 iscomponent ha port (a: instd_logic;
b: instd_logic;
sum: outstd_logic;
c_out: outstd_logic);
endcomponent;
component fa port (a, b, cin : instd_logic;
sum, c_out : outstd_logic);
endcomponent;
signal ain,s,c:std_logic_vector(3downto0) :="1111";
signal bin:std_logic_vector(3downto0):="0001";
--configuration specification forall:ha useentity work.ha(rtl);
forall:fa useentity work.fa(fa_behav);
begin
u1:ha portmap(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa portmap(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa portmap(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa portmap(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));
counter:process(clk, reset) --process(sensitivity list)beginif reset = '1'then
ain <= (others => '0');
elsif (clk'event and clk='1') then
ain <= s;
count <= s;
endif;
endprocess;
end behav_counter4;
testbench:
library ieee;
use ieee.std_logic_1164.all;
entity mycounter_testbench4 isend mycounter_testbench4;
architecture mycounter_tb4 of mycounter_testbench4 issignal count: std_logic_vector(3downto0):="1111";
signal clk: std_logic:='0';
signal reset: std_logic;
component counter4
port(count:outstd_logic_vector(3downto0):="1111";
clk:instd_logic:='0';
reset:instd_logic);
endcomponent;
begin
counter_circuit : counter4
portmap(count => count, clk => clk, reset => reset);
clock:processbeginwaitfor10ns;
clk <= not clk;
endprocess clock;
test_reset:processbeginwaitfor5ns; reset <= '1';
waitfor4ns; reset <= '0';
wait;
endprocess test_reset;
end mycounter_tb4;
> it still starts with 0001. and not 000o although ive changed the> initial values to 1111.
NOW it is time to start THINKING on your own.
Just with a few clicks in the simulator i fixed the problem with your
code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ha isport (a: instd_logic;
b: instd_logic;
sum: outstd_logic;
c_out: outstd_logic);
end ha;
architecture rtl of ha isbegin
sum <= a xor b;
c_out <= a and b;
end rtl;
----------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fa isport (a, b, cin : instd_logic;
sum, c_out : outstd_logic);
end fa;
architecture rtl of fa isbegin
sum <= a xor b xor cin;
c_out <= (a and b) or (a and cin) or (b and cin);
end rtl;
----------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter4 isport(count: outstd_logic_vector(3downto0);
clk : instd_logic;
reset: instd_logic);
end counter4;
architecture behav_counter4 of counter4 iscomponent ha port (a: instd_logic;
b: instd_logic;
sum: outstd_logic;
c_out: outstd_logic);
endcomponent;
component fa port (a, b, cin : instd_logic;
sum, c_out : outstd_logic);
endcomponent;
signal ain,s,c:std_logic_vector(3downto0) :="1111";
signal bin:std_logic_vector(3downto0):="0001";
--configuration specification forall:ha useentity work.ha(rtl);
forall:fa useentity work.fa(rtl);
begin
u1:ha portmap(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa portmap(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa portmap(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa portmap(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));
counter:process(clk, reset) --process(sensitivity list)beginif reset = '1'then
ain <= "1111"; -- Set here the initial value alsoelsif (clk'event and clk='1') then
ain <= s;
endif;
endprocess;
count <= s;
end behav_counter4;
REMIND this: because i didn't have your adders, i had to use mine.
You can do it this way also:
architecture behav_counter4 of counter4 iscomponent ha port (a: instd_logic;
b: instd_logic;
sum: outstd_logic;
c_out: outstd_logic);
endcomponent;
component fa port (a, b, cin : instd_logic;
sum, c_out : outstd_logic);
endcomponent;
signal ain,s,c : std_logic_vector(3downto0);
signal bin : std_logic_vector(3downto0) :="0001";
signal cnt : std_logic_vector(3downto0) :="0000"; -- these are the counter registers--configuration specification forall:ha useentity work.ha(rtl);
forall:fa useentity work.fa(rtl);
begin
u1:ha portmap(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa portmap(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa portmap(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa portmap(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));
counter:process(clk, reset) --process(sensitivity list)beginif reset = '1'then
cnt <= "0000";
elsif (clk'event and clk='1') then
cnt <= s; -- take over the next valueendif;
endprocess;
ain <= cnt; -- connect the counter value to the adder input
count <= cnt; -- pass to outputend behav_counter4;
Here the counter registers are explicitly declared, and therefore the
adder itself is completely combinatorial.