# Forum: µC & Digital Electronics LPC2148 I2C I2xSCH timing problem

 Author: Markus29111977 (Guest) Posted on: 2010-04-08 12:03

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Im using in my project a LPC2148 controller and have a question
concerning I2C timing. Everything works quite well but when I proofed
the timing of the I2C I discovered that the high time of the clock is
wrong. With I2xSCL/H you can adjust the high and low time (duty cycle)
of the clock. The value says how many clock cycles are used for
high/low. My PCLK runs at 60MHz (I proofed that with a PWM Output, the
frequenzy/duty cycle was exact the expected value). If I set I2xSCL/H to
75 the expected I2C data rate should be 400kHz. In reality it is about
384kHz because the high time of the clock is about 110ns too long
(1.36us instead of 1.25us). The low time fits exactly (1.25us). This
problem occurs on both I2C busses. Do you have any suggestion/experience
on this topic? Thank you for some help.

 Author: Michael M. (Guest) Posted on: 2010-04-08 12:25

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how did you measure the on time of your i2c? if it's just been measures
using an logic analyzer, you might miss some slow rising slopes due to
capacitive load on the bus lines.

 Author: Markus29111977 (Guest) Posted on: 2010-04-08 13:11

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Thanks for your answer. I measured the on time with an 100MHz 1GS/s
Oscilloscope. The on time is the time from the beginning of the rising
edge until the beginning of the falling edge. This time is too long.
That means the falling edge should start earlier. There is always the
same time offset of about 110ns (about 7 cycles@60MHz) on the on time
indepent of the value in I2xSCH. So the effect becomes more visible at
higher frequencies. The low time (beginning of falling edge until
beginning of rising edge) fits exactly. To eliminate side effects there
is no slave on the bus (only pullups) and I write a random Byte on the
bus. During this Byte-write I measure the clock timing on the bus.

 Author: Markus29111977 (Guest) Posted on: 2010-04-08 13:53
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I add a screenshot for better understanding.
Settings are:

I21SCLL = 102;
I21SCLH = 48;

So the frequenzy should be 400kHz. But as you see in the picture it is
different.

 Author: Michael M. (Guest) Posted on: 2010-04-08 14:22

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could it be that the maximum i2c frequency is limited to ~375kHz when
using 60MHz peripheral clock?
table 143 at page 147 on doc UM10139 would suggest so.
sry, that's all i got...

edit: or maybe not.
there's some errata sheet on the lpc2148 that reads an erroneous
behavior on pulse time generation for the SSP1 module.
maybe, this error occours on the i2c module also and is just not
documented yet.
you could test that by monitoring later pulses after the first 4.

errata sheet:
 SSP.1Initial data bits/clocks of the SSP transmission are shorter than subsequent pulses at higher frequencies Introduction: The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI, 4-wire SSI or a Microwire bus. The SSP can operate at a maximum speed of 30MHz and it referred to as SPI1 in the device documentation. Problem:           At high SSP frequencies, it is found that the first four pulses are shorter than the subsequent pulses. [...] Work-around: None. 

 Author: Markus29111977 (Guest) Posted on: 2010-04-08 15:27

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Thanks for your answer again. I dont´t think that I2C speed on that
controller is limited to 375kHz. At this point the datasheet can be
missunderstood. It says you must ensure that the I2C speed stays within
0 to 400kHz and that each value of I2xSCH/L must be equal or bigger than
4. So I think the 400 kHz refer to fast I2C mode spezification and the
LPC can do faster. I used 2MHz with my BMP085 pressure Sensor without
any problem. Furthermore the problem occurs at all frequencies. During
one Byte transfer all 9 clock pulses are of the same length (but too
long). I wrote to nxp technical support. Maybe they know an answer.

 Author: markus29111977 (Guest) Posted on: 2010-04-08 22:00

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Now I got an answer:

"Try with a smaller value for the pull-up resistors. Slow clock edges
cause extended pulse length."

I tried this and it worked. I reduced the pullup resistors from 4k7 to
1k2 and the I2C data rate changed (with the same settings in I2xSCH/L)
from about 384kHz to 396kHz which is very close to 400kHz. I also tried
800 Ohm and got 398kHz. So there is a dependence of the pullup resistor
and the pulse length.

 Author: Markus29111977 (Guest) Posted on: 2010-04-09 08:48
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Finally a picture of the situation with 1k2 pullups. Compare to the
picture above with 4k7 pullups (all settings in the LPC are the same).

 Author: Question (Guest) Posted on: 2011-12-01 23:41

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What values did you use for 2 MHZ?

Thanks

 Author: Question (Guest) Posted on: 2011-12-02 00:09

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The maximum I can do with 2.1 K pullup resistors is about 1.6MHZ.
I have to decrease the bus capacitance and also the pull ups.

Thanks

 Author: Question (Guest) Posted on: 2011-12-02 00:30

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Got it to 2.146 MHz!!! with same 2.1K pull ups!!!

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