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Forum: FPGA, VHDL & Verilog errors in floating point adder


Author: Mostafa Mohamed (Company: aast) (mostafa-khairy)
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Hi all,
i'm trying to design a floating point adder using advantage pro and i 
simulating it using modelsim
attached my code
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY fp_adder IS
-- Declarations
port(a,b: in  std_logic_vector(31 downto 0);
     c: out std_logic_vector(31 downto 0)
  );
END fp_adder ;

-- hds interface_end
ARCHITECTURE adder OF fp_adder IS
--declaration of sign 
signal sa,sb,sc: std_logic;
--declaration of exponent
signal tea,teb: std_logic_vector(7 downto 0);
signal ea,eb,ec: unsigned(7 downto 0);
--declaration of mantissa
signal tma,tmb: std_logic_vector(22 downto 0);
signal ma,mb,mc: unsigned(22 downto 0);
BEGIN
--asignement of sign signals
sa <= a(31);
sb <= b(31);
--assignement of exponent signals
tea <= std_logic_vector(a(30 downto 23));
teb <= std_logic_vector(b(30 downto 23));
ea <= unsigned(tea);
eb <= unsigned(teb);
--assignement of mantissa signals
tma <= std_logic_vector(a(22 downto 0));
tmb <= std_logic_vector(b(22 downto 0));
ma <= unsigned(tma);
mb <= unsigned(tmb);
------------------------------------------------------------------------------------------------------
process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
begin
  if(ea > eb)then loop
  eb <= eb+1;
  mb <= '0'& mb(22 downto 1);
  exit when ea=eb;
  end loop;
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  elsif(eb > ea) then loop
  ea <= ea+1;
  ma <= '0'& ma(22 downto 1);
  exit when ea=eb;
  end loop;
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  else
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  end if;
end process;
  c(22 downto  0) <= std_logic_vector(mc);
  c(30 downto 23) <= std_logic_vector(ec);
  c(31)        <= sc;
END adder;

and i found a problem which i couldn't recognize it
there is no error in compiling the code
but at simulation the o/p is UUUUUUUUUUUUUUUUUUUU
and there is some warnings at modelsim command window 
this is the error massage 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 

could anyone help me to solve this error
is my design synthesizable?

Author: further on not supported (Guest)
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> could anyone help me to solve this error
This is no error, it is a warning  ;-)
Try default values for your signals:
  
signal tea,teb: std_logic_vector(7 downto 0) := (others=>'0');
signal ea,eb,ec: unsigned(7 downto 0) := (others=>'0');


> is my design synthesizable?
  if(ea > eb)then loop 
No. Loops like this are not synthesisable.

Author: Mostafa Mohamed (Company: aast) (mostafa-khairy)
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thanks alot
i do what you suggest it works right when i add 0+0
but the o/p xxxxxxxxxxxx

sorry but could you advice me how to test it

Author: Duke Scarring (Guest)
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Add default values to all your internal signals.

Duke

Author: Mostafa Mohamed (Company: aast) (mostafa-khairy)
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this the new vhdl code after add a default value for all internal 
signals
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY fp_adder IS
-- Declarations
port(a,b: in  std_logic_vector(31 downto 0);
     c: out std_logic_vector(31 downto 0)
  );
END fp_adder ;

-- hds interface_end
ARCHITECTURE adder OF fp_adder IS
--declaration of sign 
signal sa,sb,sc: std_logic:= '0';
--declaration of exponent
signal tea,teb: std_logic_vector(7 downto 0):= (others=>'0');
signal ea,eb,ec: unsigned(7 downto 0):= (others=>'0');
--declaration of mantissa
signal tma,tmb: std_logic_vector(22 downto 0):= (others=>'0');
signal ma,mb,mc: unsigned(22 downto 0):= (others=>'0');
BEGIN
--asignement of sign signals
sa <= a(31);
sb <= b(31);
--assignement of exponent signals
tea <= std_logic_vector(a(30 downto 23));
teb <= std_logic_vector(b(30 downto 23));
ea <= unsigned(tea);
eb <= unsigned(teb);
--assignement of mantissa signals
tma <= std_logic_vector(a(22 downto 0));
tmb <= std_logic_vector(b(22 downto 0));
ma <= unsigned(tma);
mb <= unsigned(tmb);
------------------------------------------------------------------------------------------------------
process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
begin
  if(ea > eb)then loop
  eb <= eb+1;
  mb <= '0'& mb(22 downto 1);
  exit when ea=eb;
  end loop;
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  elsif(eb > ea) then loop
  ea <= ea+1;
  ma <= '0'& ma(22 downto 1);
  exit when ea=eb;
  end loop;
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  else
  mc <= ma+mb;
  ec <= ea;
  sc <= sa xor sb;
  end if;
end process;
  c(22 downto  0) <= std_logic_vector(mc);
  c(30 downto 23) <= std_logic_vector(ec);
  c(31)        <= sc;
END adder;

i try to test my desig my put
a =.25 "00000000101000000000000000000000"
b =.25 "00000000101000000000000000000000"
so
sa=0
sb=0
sc=0
tea=000000001
teb=000000001
ea=0000000X --i can't understand why?
eb=0000000X --i can't understand why?
tma=01000000000000000000000
tmb=01000000000000000000000
ma=0X000000000000000000000 --i can't understand why?
mb=0X000000000000000000000 --i can't understand why?
mc=XXXXXXXXXXXXXXXXXXXXXXX but i expect to be ="10000000000000000000000"

plz can you explain why there's unknown bits?

Author: Duke Scarring (Guest)
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Try type conversion without temporary signals, like here:
--assignement of exponent signals
ea <= unsigned(a(30 downto 23));
eb <= unsigned(b(30 downto 23));
--assignement of mantissa signals
ma <= unsigned(a(22 downto 0));
mb <= unsigned(b(22 downto 0));

Duke

P.S.: I suggest to use records:
type float_t is record
  s: std_logic;
  e: unsigned(7 downto 0);
  m: unsigned(22 downto 0);
end record;
You can use it like: c.m <= a.m + b.m;

Author: Andreas Schwarz (andreas) (Admin) Flattr this
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There are some fundamental problems in your code. Is this supposed to be 
a clocked or combinatorial adder? Because at the moment it is neither. 
You have signals that are not assigned in every branch, signals that are 
assigned their previous values, loops with non-constant exit conditions 
- all that will blow up when you try to synthesize it. I suggest you 
follow the rules in http://embdev.net/articles/VHDL and look at some 
examples.

Author: Ras Funk (rasfunk)
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If you just need a FPAdder, try FloPoCo:

http://www.ens-lyon.fr/LIP/Arenaire/Ware/FloPoCo/

It's VERY advanced, you can customize all parameters such as pipeline 
depth, mantissa width, internal representation, ...

What you get is a perfectly synthesizable VHDL entity.

Plus it's free!

Author: Mostafa Mohamed (Company: aast) (mostafa-khairy)
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@ Andreas Schwarz
thanks for your help but sorry i'm new at vhdl could u explain to me 
what's record and how can i use it i'm trying to read about it from vhdl 
by example but i understand nothing.

@ Ras Funk
thanks alot for your post but i have to do it by myself coz i'll use it 
at my graduation project

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