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Forum: FPGA, VHDL & Verilog FPGA development resources


Author: Andreas Schwarz (andreas) (Admin) Flattr this
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CPLD or FPGA?

The main difference is that CPLDs are smaller than FPGAs, i.e. you can fit a lot more logic inside a FPGA than inside a CPLD.

  • CPLDs: address decoders, bus interfaces, simple memory controllers, (video) signal generators
  • FPGAs: complex CPUs, high speed I/O, signal processing, encryption

VHDL or Verilog?

The difference is mainly in syntax, you can get the same synthesis result with both languages. VHDL is more verbose than Verilog (which can be an advantage or disadvantage, depending on how you look at it). In Europe VHDL is much more widely used than Verilog, in the US Verilog seems to be slightly more popular.

Basic rules for VHDL development

See http://embdev.net/articles/VHDL.

Chip vendors

Boards

  • also see the FPGA vendors’ websites
  • Digilent

Tutorials

  • TODO

IP Cores

  • Opencores – CPUs, USB, Ethernet, encryption, …

If you want to suggest any additions to this post, please reply below.


Author: Juha (Guest)
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Hi,

I think this site would be helpfull. Here is some basic things and some 
more advanced.
http://www.fpga4fun.com/

Author: Shahul Akthar (Company: pantech solution) (shahulakthar)
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Here is a Source for learning FPGA and VHDL concepts

http://allaboutfpga.com/

Author: René D. (Company: www.dossmatik.de) (dose)
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for verfication

http://www.stefanvhdl.com/


a good simulator is the combination GHDL and GTKwave

http://sourceforge.net/projects/ghdl-updates/
http://gtkwave.sourceforge.net/



I have written an introduction for this simulator
http://www.dossmatik.de/ghdl/ghdl_unisim_eng.pdf

Author: Warren Toomey (doctorwkt)
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I found the book "Free Range VHDL" to be an excellent book about the 
language and also about best practices when writing VHDL code. Link:
http://freerangefactory.org/shop.html#FreeRangeVHDL-Book

Cheers, Warren

Author: mister (Guest)
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<script>window.alert("test")</script>

Author: mister (Guest)
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<script>window.alert("test")</script>

Author: Alishan Ahmed (alishan)
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What would be the code to generate a clock multiplier for Altera using 
FPGA ?

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