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Forum: FPGA, VHDL & Verilog Partial Reconfiguration


von Prasad M. (Company: Student) (renuprasad)


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Hi... I want to know how to implement the BIST logic on virtex-5 fpga 
using Partial Reconfiguration.. In that what should be the static logic 
and what should be reconfigurable logic.. How to map our logic using 
plan ahead.. Thanks in advance.........

von Duke Scarring (Guest)


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> In that what should be the static logic
> and what should be reconfigurable logic..
That depends on your requirements.

> How to map our logic using plan ahead..
I think partial reconfiguration is an academical topic.
Take a look at the manual of planahead how and if it support partial 
reconfiguration.
Also ask Xilinx: http://www.xilinx.com/tools/partial-reconfiguration.htm

Duke

von Br i. (brian_w17)


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You actually need to designate reconfigurable modules which can be 
reconfigured.

I'd start here:
http://www.xilinx.com/itp/xilinx7/books/data/docs/dev/dev0038_8.html

von netb (Guest)


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You also need a special licence from Xilinx to use partial 
reconfiguration with PlanAhead. It isn't cheap as far as I know... but 
if you are a student you can ask your professor to get in contact with 
the Xilinx University program. In this program, Xilinx maybe give you an 
academic licence for a symbolic donation.

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