I have written a verilog code using 'for' loop..My aim is to display 2,3,4 in three consecutive clock cycle.But for the first clock cycle itself,my 'for' loop is executing fully and showing output as 4.How can I avoid this?? (I studied that for loop will execute sequentially only.But I am not getting output sequentially.) I am including my code below...Plz help me... module for_test(clk,n,m); //programe for testing the for loop input clk; output [7:0] m; output n; reg [7:0] m; integer n; always @(posedge clk) begin for(n=2;n>=0;n=n-1) begin if(n==2) begin m <=8'h02; end else if(n==1) begin m <=8'h03; end else if(n==0) begin m <=8'h04; end end end endmodule
The for statement is executing sequentially but within one clock cycle as you coded it above. It should be completely forbidden for beginners to use any loop statements in Verilog or VHDL because they won't do what you'd expect from a programming language. What you want to be implementing is a counter. Search the internet, there are thousands of examples how it works. http://www.asic-world.com/ contains a lot of examples.
ok..then how can i modify the above program so that the for loop will execute only one iteration for each clock..... PLZ help me....thanks for ur reply
YOu must implement a counter and then select one of the output values according to the counters value:
1 | reg [7:0] m; |
2 | reg [1:0] n := 2'h02; -- initialize the counter |
3 | |
4 | always @(posedge clk) begin |
5 | n <= n-2'h01; -- thats the counter |
6 | if(n==2'h02) begin |
7 | m <=8'h02; |
8 | end
|
9 | if(n==2'h01) begin |
10 | m <=8'h03; |
11 | end
|
12 | if(n==2'h00) begin |
13 | m <=8'h04; |
14 | end
|
15 | end
|
I'm sorry, if the code doesn't work directly (I'm a VHDL fellow), but hopefully you get the idea... ;-)
So i want to replace my for loop with if statement.. Is there any method to use for loop itself?? That means any logical method that execute one iteration of a for loop in one clock cycle???
> So i want to replace my for loop with if statement.. No, you must replace it by a state machine! Everything in hardware (FPGA) that has a "one after the other" must be a state machine. And the most simple kind of a state machine is a counter, counting one step after the other... > Is there any method to use for loop itself?? Not for that, waht you want to do. You can use a loop e.g. if you want to write only one inverter (or something else) and you want to get lots of inverters in parallel on the FPGA...
Lothar Miller wrote: >> So i want to replace my for loop with if statement.. > No, you must replace it by a state machine! Everything in hardware > (FPGA) that has a "one after the other" must be a state machine. And the > most simple kind of a state machine is a counter, counting one step > after the other... > >> Is there any method to use for loop itself?? > Not for that, waht you want to do. > You can use a loop e.g. if you want to write only one inverter (or > something else) and you want to get lots of inverters in parallel on > the FPGA... Actually above code is only a sample...I want to include a block of statements in each iteration that i want to execute sequentially in each clock cycle..If i go for state machine i want to replicate my code for each state and code length become very large...Thats why i am asking about for loop that execute sequentially like a state machine!!!
> Thats why i am asking about for loop that execute sequentially > like a state machine!!! To keep things short: such a loop does not exist. > I want to include a block of statements in each iteration that i want > to execute sequentially in each clock cycle.. What is your actual problem?
Lothar Miller wrote: >> Thats why i am asking about for loop that execute sequentially >> like a state machine!!! > To keep things short: such a loop does not exist. > >> I want to include a block of statements in each iteration that i want >> to execute sequentially in each clock cycle.. > What is your actual problem? In my design all the iterations of for loop is executing in one clock edge.... I want a for loop which will execute one iteration in one clock edge...That means in first rising edge of clock,it should execute first iteration of for loop.In second rising edge of clock,it should execute 2nd iteration of for loop like wise it should continue.... thanks for ur replies!!!!
> I want a for loop which will execute one iteration in one clock edge... Then you can't use Verilog. Because loops in Verilog don't offer the desired behaviour! To say it in a different way: a loop in Verilog is not capable to do what you want. > In my design all the iterations of for loop is executing in one clock > edge.... Thats exactly the way a loop in Verilog is expected to work. Is it really that hard to understand? :-o I already told the solution everybody else in the world uses: FSM https://www.google.de/search?q=verilog+fsm
Im trying to write a verilog code for this expression as an assignment.. anyone who knows about it please help.. thanks in advance
Blue wrote: > Im trying to write a verilog code for this expression as an > assignment.. > anyone who knows about it please help.. thanks in advance for i=1:H for j=1:W k(i,j) = (1-(2*i/(R*H)-1/R)^2-... (2*j/(R*W)-1/R)^2); if k(i,j) < 0 k(i,j) = 0; end end end end
Shahid wrote: > how to fix my error 1440 in verilog code Read about "loops in Verilog". They do not what you (or any other C-programmer) expect... > how to fix my error 1440 in verilog code Try it with a fixed range in the loop and terminate the loop prematurely. BTW: it is a very, very clever idea to post source code NOT as a screenshot. It is very, very difficult to apply some changes or even copy a line out of that kind of "code". BTW2: pls start a NEW thread for a NEW question. BTW3: did you read the thread ahead of your post. Did you read the thing about the different behaviour of loops?
module for_test(clk,n,m); //programe for testing the for loop input clk; output [7:0] m; output [2:0] n; reg [7:0] m; reg [2:0] n; always @(posedge clk) begin if (n>0) n <= n-1; case(n) 2: m <= 2; 1: m <= 3; 0: m <= 4; endcase end initial begin n = 2; end endmodule
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