I am new to this subject and am having trouble understanding this topic.
Suppose I have the following circuit to control the forwarding of a MIPS 
pipeline processor:
[![enter image description here][1]][1]

So the forwarding control will be in the EX stage because the ALU 
forwarding multiplexors are found in that stage.
These are the control values for the forwarding multiplexors :
[![enter image description here][2]][2]


The goal here is to deal with the data hazards and to pass proper values 
early from the pipeline registers to ALU rather than writing for the WB 
stage to write the register file.
This is the truth table that I have for this circuit : I filled some of 
the cases
[![enter image description here][3]][3]
[![enter image description here][4]


  [1]: https://i.stack.imgur.com/K4Z3C.png
  [2]: https://i.stack.imgur.com/72NGX.png
  [3]: https://i.stack.imgur.com/PO1QX.png
  [4]: https://i.stack.imgur.com/zvsk4.png

How exactly are the output signals ForwardA and ForwardB selected when 
EX/MEM and MEM/WB at 1 and WBHazardRt at 1 ?