Forum: FPGA, VHDL & Verilog Digital Clock Manager

von Divya P. (Company: IIA) (div_01)

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I want to maintain constant frequency of 50MHz for my Nexys A7 FPGA. 
Currently, the internal clock is 100MHz. How can I implement a digital 
clock manager in VHDL/Verilog to make sure my frequency is reduced to 
50MHz and maintains the same throughout?

Thanks & Regards,

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Read the documents and manuals of the FPGA mounted on the board. The 
Xilinx UG472 includes templates in VHDL and Verilog for the Artix 7.

von Divya P. (Company: IIA) (div_01)

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Thank you for the reply. I could maintain the desired clock output by 
making use of clock wizard in IP catalog in Vivado.


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