Hi, I want to maintain constant frequency of 50MHz for my Nexys A7 FPGA. Currently, the internal clock is 100MHz. How can I implement a digital clock manager in VHDL/Verilog to make sure my frequency is reduced to 50MHz and maintains the same throughout? Thanks & Regards, Divya
Read the documents and manuals of the FPGA mounted on the board. The Xilinx UG472 includes templates in VHDL and Verilog for the Artix 7.
Thank you for the reply. I could maintain the desired clock output by making use of clock wizard in IP catalog in Vivado.