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Forum: FPGA, VHDL & Verilog Creating csync for external pixelbus


von Joey O. (nasdrasil)


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Hey guys!

After a little bit of doubt (I don't have much experience using fpga's) 
I decided to post my question here...

I have a retro computer that I'd like to RGB mod by using an IC40 HX8K.

I have been experimenting quite a bit and have done the following:

- Mapped out the original color PROMS of the system so I have all known 
input and corresponding output bits.
- Scoped out the internally created sync to measure front porch, back 
porch etc. Basically mapped out all the timings.
- Found out that serration pulses are missing in the internally created 
Csync signal, making this signal unusable since it will not work with 
some tv's or scalers.

After this I started using Verilog to code and experiment. I use 
Icestudio to create codeblocks. I thought to start with modeling a piece 
of ROM that mimics the original PROM of the computer to output the RGB 
pixel data from my fpga. This works fine and I am confident that what I 
see on my scope as output from the fpga is corresponding to the data the 
computer outputs to form pixels on the screen. From this I conclude that 
my RGB pixel output is correct and my modeled ROM is creating pixel data 
the way the original PROM does.

I then proceded to create an appropriate sync signal with correct 
timings. This was not super difficult since I had all the timings scoped 
out already. As a template I used one of the many VGA controller 
tutorials available online and I adapted this for my needs. When I 
review my work on my scope I can see a csync signal that corresponds to 
the timings that I need.

Now... I am feeding the system clock (4Mhz) to the modeled ROM and also 
use it as a way to creat sync, both modules (modeled ROM and sync 
creation) are on thesame clock. The thing is that when I review my 
signals on my scope I find that there is a random time difference 
between sync signal and my pixel data on every power-up or reset.

When I power-up the systemp I always have sync ahead or behind the pixel 
data. It never matches up and it is never thesame amount of time-shift. 
I added a picture of my scope which shows Vsync in yellow and pixel data 
in blue for reference. As you can see... Vsync is ahead.

I was wondering whether my general approach is ok, or if should use a 
different one. I have thought about creating a signal with a pulse that 
triggers the sync counter at the right time. I have been able to create 
that signal out of the pixel data, as is shown in my added picture in 
purple. The rising edge of this tiny little negative pulse matches up 
exactely with the position where Vsync is supposed to be, but I am 
unable to actualy make sync start in that location.

I was just wondering what it could be that makes for this time 
difference. I find all sorts of guides on creating Sync and pixel data 
inside an fpga, but there seems to be almost no documentation (at least 
not that I can find) on how to bring a pixel bus from an external system 
into an fpga and recreate a sync signal with the systems clock to 
accompany it.

If my question seems like a beginners one or if I have not provided 
enough information then let me know. I was just wondering where the time 
difference could come from, and if I am approaching this project in the 
right way, or if I should go about it in a completely different 
approach.

To anyone who made it this far... thanks for reading! :-)

von FPGA Notfallseelsorge (Guest)


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Code or it didn't happen.

von Joey O. (nasdrasil)


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Alright, so some code. Here is the part I use to model the color PROM of 
the original machine. I also use D4 (it's a 5 bit address bus I'm 
tapping into) to create a startpulse for sync. The timing of this 
startpulse is locked on to the output rgb data and so it creates the 
purple negative pulse as show in my opening post. I was wondering if I 
could use this as some sort of sync enable/start pulse.

Icestudio lets you create any inputs and outputs visually so I don't 
code these.
1
    //-- COLOR ROM memory
2
    reg [2:0] red_rom [16:0];
3
    reg [2:0] green_rom [16:0];
4
    reg [2:0] blue_rom [16:0];
5
    
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    //-- RGB pixel buses  (3 bits)
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    reg [2:0] RED;
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    reg [2:0] GREEN;
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    reg [2:0] BLUE;
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    //-- Address bus (5 bits)
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    wire [4:0] A;
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    //-- Synchronize CS to data
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    reg startpulse;
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    reg [12:0] countD4;
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18
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    //counter while D4 is high
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    always @ (posedge clk)
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        begin
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            if (A[4] <= 0) 
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            countD4 = 0;
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            else
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            countD4 = countD4 + 1;
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        end
27
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    //position of sync pulse start (use as EN signal for sync?)
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    always @ (posedge clk)
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        begin
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            if (countD4 == 6399) 
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            startpulse <= 1;
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            else 
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            startpulse <= 0;
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        end 
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37
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    always @(posedge clk) 
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        begin
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            RED [2:0] <= red_rom[A];
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            GREEN [2:0] <= green_rom[A];
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            BLUE [2:0] <= blue_rom[A];
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        end
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45
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    //-- Memory contents read from the ROMFILE file
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    initial begin
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        if (R) $readmemb(R, red_rom);
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        if (G) $readmemb(G, green_rom);
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        if (B) $readmemb(B, blue_rom);
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    end
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    assign Sync_start = ~startpulse;

This next part is what I use to create Sync and Blanking.
1
//-- sync generation
2
    reg [9:0] CounterX;
3
    reg [9:0] CounterY;
4
    reg HS, VS;
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    reg BLANK;
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    wire CounterXmaxed = (CounterX == 255); // 207 + 5 + 19 + 24
8
    wire CounterYmaxed = (CounterY == 311); // 286 + 3 + 3 + 19
9
    
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    // -- SYNC GENERATION ---------------------------------
12
    always @(posedge clk) 
13
    begin
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        if (EN) 
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            begin
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                if (CounterXmaxed)
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                CounterX <= 0;
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                else
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                CounterX <= CounterX + 1;
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            end
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        else CounterX <=0;
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    end
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    always @(posedge clk)
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    begin
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        if (CounterXmaxed)
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            begin
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                if (CounterYmaxed)
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                CounterY <= 0;
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                else
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                CounterY <= CounterY + 1;
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            end
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    end
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    always @(posedge clk)
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    begin
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      HS <= (CounterX > (206 + 5) && (CounterX < (206 + 5 + 20)));   // active for 19 clocks
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      VS <= (CounterY > (286 + 3) && (CounterY < (286 + 3 + 4)));   // active for 3 lines
40
    end
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    //--------------------------------------------------------
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43
    
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    //-- Blanking --------------------------------------------
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    always @(posedge clk)
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    begin
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      if ((CounterY <= 286) && (CounterX <= 206)) 
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         begin
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         BLANK <= 1;
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         end else begin 
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         BLANK <= 0;
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         end    
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    end
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    //--------------------------------------------------------
55
    
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    assign Hor = ~HS;
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    assign Ver = ~VS;
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    assign BLANKING = BLANK;

These seperate parts of code seem to do exactely what I want, but as 
said the timing of sync is always off by a random amount. It's not that 
I am looking for a ready made solution. I'd like to use this project to 
learn so if anybody has cosntructive tips or links to websites that 
describe what I should know to continue that would be much appreciated 
:-)

von FPGA Notfallseelsorge (Guest)


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The counters have no initial value. So they start counting at an 
arbitrary value which just happens so be in the uninitialized registers.

Note:
Xilinx sets these registers to zero.

von Joey O. (nasdrasil)


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So... a simple

reg [9:0] CounterX = 0;
reg [9:0] CounterY = 0;

would suffice?

von FPGA Notfallseelsorge (Guest)


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Maybe ... give it a try.

von Joey O. (nasdrasil)


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Tried the above, also tried adding
1
initial begin
2
CounterX = 0;
3
CounterY = 0;
4
end

No avail. I still keep getting a random timing difference between pixel 
data and sync. I added a global reset (signal pulled from the retro 
machine) and this works fine. Pixel data and sync signals are all reset. 
But again... with a random time difference. If it is what you said it is 
(random reg initial state) I think I will have to find how to set this 
to 0 in the fpga I have. At least it's a start on where to look :-)

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