Anyone to help me with this task, please?
Develop a VHDL model of the PULSE TIMER component that will have the
following interface:
fclk - FPGA clock,
out - timer output,
delay - time delay in µs after which the timer starts to generate
rectangular pulses,
width - time of generating rectangular pulses in µs,
period - period of rectangular pulses in µs.
sflag - status bit that indicates to the top model that the pulse
generation process is complete. Bit sets to 1 for a period of 5 µs after
which it switches to state 0.
Assume that the value of the signal width is an integer product of the
period.
Test the TIMER component by implementing a testbench program that will
generate pulses after 105 µs, duration 50 µs and periods 10 µs.
-All models are called top.
-Top model in testbench is called top_tb.
-FPGA clock is 100MHz.