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Forum: FPGA, VHDL & Verilog package and procedure


von Dang T. (Company: hust) (tien_newbie)


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I have made a small example of the package and procedure but the error 
shows an error. Unit is not declared. I tried but can't fix it.

von fpgakuechle (Guest)


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See below (also attached), maybe just the last line misses some 
keywords. Pleas contribute full error message/log.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package package_Thong_so is
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--- Thong so mach luc
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  constant one_div_Lf    :    signed(12-1 downto 0) := to_signed(200, 12);    --Lf = 5e-3
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  constant one_div_Cf    :    signed(18-1 downto 0) := to_signed(66667, 18);  --Cf = 15e-6
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  constant Vdc           :    signed(11-1 downto 0) := to_signed(180, 11);    --Vdc_1cell = 180
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  constant N             :    signed(5-1 downto 0)  := to_signed(1, 5);
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--constant Ts: signed(22-1 downto 0) := to_signed(21,22);
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  subtype unit is signed(22-1 downto 0);
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  procedure Tinh_toan(Ts : in unit;
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                      Ts_div_Cf, Ts_div_Lf, W_Ts, Vdc_Ts_3Lf : out unit);
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end package;
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-- tinh toan phan tu ma tran
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package body packgage_Thong_so is
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  procedure Tinh_toan(Ts : in unit;
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                      Ts_div_Cf, Ts_div_Lf, W_Ts, Vdc_Ts_3Lf : out unit) is
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    variable temp_Ts_div_Cf  : signed(40-1 downto 0);
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    variable temp_Ts_div_Lf  : signed(34-1 downto 0);
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    variable temp_Vdc_Ts_3Lf : signed(61-1 downto 0);
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  begin
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    temp_Ts_div_Cf  := Ts * one_div_Cf;
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    Ts_div_Cf       := temp_Ts_div_Cf(temp_Ts_div_Cf'high) & temp_Ts_div_Cf(39-1 downto 18);
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    temp_Ts_div_Lf  := Ts * one_div_Lf;
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    Ts_div_Lf       := temp_Ts_div_Lf(temp_Ts_div_Lf'high) & temp_Ts_div_Lf(33-1 downto 12);
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    w_Ts            := to_signed(6588, 22);
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    temp_Vdc_Ts_3Lf := Ts * Vdc * one_div_Cf * to_signed(171, 10);
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    Vdc_Ts_3Lf      := temp_Vdc_Ts_3Lf(temp_Vdc_Ts_3Lf'high) & temp_Vdc_Ts_3Lf(60-1 downto 39);
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  end procedure;
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end;  -- try end package body here!!

von fpgakuechle (Guest)


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See for syntax on package, package body, and procedure :
https://www.ics.uci.edu/~jmoorkan/vhdlref/procedur.html

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