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Forum: FPGA, VHDL & Verilog Executing ONERROR command at macro ./halfadder_simu.do line 6


von RAMA (Guest)


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module half_adder
  (
   i_bit1,
   i_bit2,
   o_sum,
   o_carry
   );

  input  i_bit1;
  input  i_bit2;
  output o_sum;
  output o_carry;

  assign o_sum   = i_bit1 ^ i_bit2;  // bitwise xor
  assign o_carry = i_bit1 & i_bit2;  // bitwise and

endmodule // half_adder

von Lothar M. (lkmiller) (Moderator)


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What's the problem?
Is the unknown toolchain installed properly?
Can you simulate anything else?

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