I'm looking for a way to assign (or change) certain values to (of) my signals during a VHDL simulation. For example I'd like to pause the simulation, change the values of my state machine and continue with the new values. Is that possible? I'm aware that you can give signals initial values, however, these values are deleted during reset. Furthermore it would mean that I had to change all of my VHDL sources - something I'd like to avoid. What I actually try to to is to investigate the behaviour of a state machine I implemented in an FPGA when I feed in the data from my ADCs. The system is not behaving in the way I wanted, so I used the integrated logic analyzer from Vivado to store the ADCs samples I got + the state variables of my control system. I now would like to recreate the exact same situation in the simulator to see what is going on in the control logic. Any ideas?
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Something like force/release in Verilog? There is also a TCL command (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug835-vivado-tcl-commands.pdf page 62) if that helps. If you use VHDL2008 I think there is a force/release keyword as well.
That will do the job I guess, thanks a lot. Unfortunately I have to use this from the tcl console and can't use it in the VHDL testbench directly (apparently Vivado doesn't support the force release keywords from VHDL 2008) but it will suffice.
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