# Forum: FPGA, VHDL & Verilog ice40HX8k enable signal from clock

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Hi,
I hope my subject is correct for what I am trying to achieve. My task is
to write an error detection latch on the board mentioned in my title.
For that latch I need to write a signal called detection window(dw). The
clock is the system clock at 12MHz. dw needs to rise 1/4 period after
clock has risen and stay high for the rest of the period:
clk__--__--__--
dw --_---_---_-
I wanted to use the PLL for my target behaviour. My idea was to write
sth in code that would use an even number of inverters to delay the
clock signal by 1/4 of a period. Then I would write assign dw =
NOT(clk)OR(clk_4) wiht clk_4 being the delayed clock. Then the PLL
should align dw and clk so that dw rises 1/4 period after clk has risen.
My first attempt was to write the module with parameters. This works
great for simulation but turns out as trash after synthesis, simply
assigning a 1 to dw.
Problem is that the device has no inverters and the delay of a LUT which
would be used as an inverter is like 0.3 ns according to timing analysis
which means most of the delay comes from wiring which I can not control,
right?
Is this even the correct way to do it or can someone help me with a
better way to do this? I am using Icecube and/or yosys with nextpnr. Any
help is appreciated.

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Hi Fabian,

For various reasons, the correct way to approach FPGA design is to
think synchronous, with the overall design driven by one global clock,
perhaps generated by a PLL. This is not to say that asynchronous
intermediate logic is bad; I use it all the time.

Use edge-clocked registers (not latches) to store logic results, e.g.
always @(posedge clk) ... (normal default)
always @(negedge clk) ... (also valid)

Rethink your implementation so that the troublesome dw latch enable and
error latch go away.

FPGAs are not meant to implement asynchronous delay elements, latches,
gated clocks, or other abominations from the bad old days of jellybean
design habits.

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