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Forum: FPGA, VHDL & Verilog Double Data Rate Serializer verilog


von Atalin (Guest)


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Hi! I want to write the code for a serializer which works both on rising 
edge and falling edge of the clock. The idea is to write two registers, 
one for the even bits and the other one for the odd bits, and then a MUX 
which send out the data. Moreover, I have a control signal called LOAD: 
when LOAD is high, I want to load the data into the two registers. The 
problem is that the even bits are not loaded into the register and I do 
not know why because I wrote the same piece of code both for the odd 
bits and the even ones. Can anyone help me? Thank you very much! The 
code is hereinafter.
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module serializer (data_in, send, clk, load, rst, data_out);
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input wire [11:0] data_in;
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input wire send, clk, load, rst;
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output reg data_out;
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reg [7:0] temp_data_out_even;
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reg [7:0] temp_data_out_odd;
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integer i;
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integer j;
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always @ (posedge clk) 
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begin
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  if (rst) begin
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    data_out <= 1'b0;
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    temp_data_out_odd <= 8'b00000000;
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  end
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  else if (load) begin
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    temp_data_out_odd <= 8'b11000000;
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    for(i=0; i<6; i=i+1)
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      temp_data_out_odd[5-i] <= data_in[11-i*2];
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  end
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  else if (send) begin
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    data_out <= temp_data_out_odd[7];
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    temp_data_out_odd <= {temp_data_out_odd[6:0], 1'b0};  // Shifting phase
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  end
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end
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always @ (negedge clk) 
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begin
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  if (rst) begin
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    data_out <= 1'b0;
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    temp_data_out_even <= 8'b00000000;
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  end
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  else if (load) begin
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    temp_data_out_even <= 8'b00000000;
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    for(j=0; j<6; j=j+1)
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      temp_data_out_even[5-j] <= data_in[10-i*2];
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  end
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  else if (send) begin
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    data_out <= temp_data_out_even[7];
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    temp_data_out_even <= {temp_data_out_even[6:0], 1'b0};  // Shifting phase
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  end
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end
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endmodule //end module serializer

The testbench is the following
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`include "serializer.v"
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`timescale 1ns / 1ps
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module serializer_tb();
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// Declare inputs as regs and outputs as wires
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reg [11:0] data_in;
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reg send, clk, load, rst;
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wire data_out;
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reg [11:0] reg_sipo;
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reg check;
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integer i;
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// Initialize all variables
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initial begin          
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  clk = 1;       // initial value of clock
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  rst = 1;       // initial value of reset
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  load = 0;
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  send = 0;
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  #15 rst = 0;   // De-assert the reset
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  forever begin
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    foreach(data_in[j]) data_in[j] = $urandom;
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    #13 load = 1;
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    #20 load = 0;
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    #5 send = 1;
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    #20          //header
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    for(i=0; i<12; i=i+1) begin
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      #5 reg_sipo[11-i] <= data_out;
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      end
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    #10 send = 0;
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    if(reg_sipo == data_in) check = 0;
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    else check = 1;
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  end
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end
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// Clock generator
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always begin
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  #5 clk = ~clk; // Toggle clock every 5 ns - 100 MHz
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end
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// Connect DUT to test bench
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serializer U_serializer (data_in, send, clk, load, rst, data_out);
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endmodule

von Alexx (Guest)


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I am not really a verilog user but can you write on a signal from two 
different processes? in VHDL you cannot.

von -gb- (Guest)


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You should could use a DDR IO Primitive from the FPGA Vendor. Like ODDR2 
from Xilinx.

But ... no, not write from two processses, but read.

Registers A for rising edge and B for falling edge. And some logic which 
provides new data for BOTH registers.

So the logic (with whatever clock) provides new data for both registers. 
And sets a data valid signal.
With rising edge logic, the data valid signal is detected and the 
provided data is written to reg A.
With falling edge logic, the data valid signal is detected and the 
provided data is written to reg B.

von Ian Tseng (Guest)


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I think

    for(j=0; j<6; j=j+1)
      temp_data_out_even[5-j] <= data_in[10-i*2];

Should be
    for(j=0; j<6; j=j+1)
      temp_data_out_even[5-j] <= data_in[10-j*2];


10-i*2 => 10-j*2

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