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Forum: FPGA, VHDL & Verilog How powerful is Verilog at using parameters to specify designs?


von Kevin S. (kvnsmnsn)


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I have a design in mind that would fit in this skeleton:
module xyz ( result, leftOp, rightOp);
parameter  integer nmBits = 1;
localparam integer highBit = nmBits - 1;
output             result;
input [ highBit:0] leftOp;
input [ highBit:0] rightOp;

// ...

endmodule
The way (xyz) is designed, this module would work differently for 
different values of (nmBits), but in a way that can be precisely 
defined. In fact, I'm seriously thinking of writing a Java program that 
takes (nmBits) as an input and produces a parameterless verion of (xyz) 
for that version of (nmBits). So I'm wondering, is it a true statement 
that, if one can write such a Java program to produce the equivalent 
(parameterless) Verilog code for any given set of parameters, one can 
also write Verilog code with parameters to do the same thing?

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