EmbDev.net

Forum: FPGA, VHDL & Verilog warning: Static variable initialization requires explicit lifetime in this context


warning: Static variable initialization requires explicit lifetime in this context
von Kevin S. (kvnsmnsn)

Rate this post
• ▲ useful
▼ not useful 
I've got a Verilog compilation complaint that I've been able to isolate 
in a stripped down version of my code:
1
module expLif ();

2
parameter  integer nmBits  = 1;

3
localparam integer highBit = nmBits - 1;

4
output             lssThn;

5
input [ highBit:0] leftOp;

6
input [ highBit:0] rightOp;

7
8
typedef enum { CORNER, E_LEAF, N_LEAF, SIDE, E_INTERIOR, N_INTERIOR } nodeType;

9
typedef struct packed

10
{ nodeType ndType;

11
   integer inLow;

12
   integer inHigh;

13
   integer out;

14
} node;

15
16
localparam integer nmNodes  = 2 * nmBits - 1;

17
localparam integer nmLevels = $clog2( nmBits) + 1;

18
19
localparam integer [ nmLevels:0] bases;

20
21
initial

22
23
begin

24
  integer lvl;

25
  integer pwr = 1;

26
  bases[ 0]   = 1;

27
  for (lvl = 1; lvl <= nmLevels; lvl = lvl + 1)

28
  begin

29
    bases[ lvl] = bases[ lvl - 1] + ((nmNodes + pwr >> lvl << 1) - 1);

30
    pwr       <<= 1;

31
  end

32
end

33
34
endmodule

The actual complaint when I try to simulate this with Icarus is:
1
D:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o expLif.vvp expLif.sv

2
expLif.sv:19: syntax error

3
expLif.sv:19: error: syntax error localparam list.

4
expLif.sv:25: warning: Static variable initialization requires explicit lifetime in this context.

5
6
D:\Hf\Verilog\Unpacked\Src\Common>

I want value (pwr) to be successive powers of two each time I go through 
one iteration of the loop. Can anyone tell me why this code doesn't work 
and/or what I need to do to fix it? Thanks in advance for any 
suggestions you can give me.

  


  




  

    Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
  







      

      



  

    Re: warning: Static variable initialization requires explicit lifetime in this context
  


  

    

      von
      
        Klakx (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
I think the error is more important.

Try this
localparam integer  bases [ nmLevels:0];

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: warning: Static variable initialization requires explicit lifetime in this context
  


  

    

      von
      
        Kevin S.
        (kvnsmnsn)
        
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Klakx: "I think the error is more important. Try this localparam integer 
bases [ nmLevels:0];" I'm fine with fixing the error before dealing with 
the warning. But I
made the change you suggested:
1
module expLif ();

2
parameter  integer nmBits  = 1;

3
localparam integer highBit = nmBits - 1;

4
output             lssThn;

5
input [ highBit:0] leftOp;

6
input [ highBit:0] rightOp;

7
8
typedef enum { CORNER, E_LEAF, N_LEAF, SIDE, E_INTERIOR, N_INTERIOR } nodeType;

9
typedef struct packed

10
{ nodeType ndType;

11
   integer inLow;

12
   integer inHigh;

13
   integer out;

14
} node;

15
16
localparam integer nmNodes  = 2 * nmBits - 1;

17
localparam integer nmLevels = $clog2( nmBits) + 1;

18
19
localparam integer bases [ nmLevels:0];

20
21
initial

22
23
begin

24
  integer lvl;

25
  integer pwr = 1;

26
  bases[ 0]   = 1;

27
  for (lvl = 1; lvl <= nmLevels; lvl = lvl + 1)

28
  begin

29
    bases[ lvl] = bases[ lvl - 1] + ((nmNodes + pwr >> lvl << 1) - 1);

30
    pwr       <<= 1;

31
  end

32
end

33
34
endmodule

and then when I used Icarus to attempt to simulate it I got:
1
E:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o expLif.vvp expLif.sv

2
expLif.sv:19: syntax error

3
expLif.sv:19: error: syntax error localparam list.

4
expLif.sv:25: warning: Static variable initialization requires explicit lifetime in this context.

5
6
E:\Hf\Verilog\Unpacked\Src\Common>

so the change you suggested doesn't appear to have fixed the error. Do 
you have any other ideas on what might be causing the error and/or how I 
can fix it? Anybody know what I'm doing wrong here?

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.