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Forum: FPGA, VHDL & Verilog warning: Static variable initialization requires explicit lifetime in this context


von Kevin S. (kvnsmnsn)


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I've got a Verilog compilation complaint that I've been able to isolate 
in a stripped down version of my code:
module expLif ();
parameter  integer nmBits  = 1;
localparam integer highBit = nmBits - 1;
output             lssThn;
input [ highBit:0] leftOp;
input [ highBit:0] rightOp;

typedef enum { CORNER, E_LEAF, N_LEAF, SIDE, E_INTERIOR, N_INTERIOR } nodeType;
typedef struct packed
{ nodeType ndType;
   integer inLow;
   integer inHigh;
   integer out;
} node;

localparam integer nmNodes  = 2 * nmBits - 1;
localparam integer nmLevels = $clog2( nmBits) + 1;

localparam integer [ nmLevels:0] bases;

initial

begin
  integer lvl;
  integer pwr = 1;
  bases[ 0]   = 1;
  for (lvl = 1; lvl <= nmLevels; lvl = lvl + 1)
  begin
    bases[ lvl] = bases[ lvl - 1] + ((nmNodes + pwr >> lvl << 1) - 1);
    pwr       <<= 1;
  end
end

endmodule

The actual complaint when I try to simulate this with Icarus is:
D:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o expLif.vvp expLif.sv
expLif.sv:19: syntax error
expLif.sv:19: error: syntax error localparam list.
expLif.sv:25: warning: Static variable initialization requires explicit lifetime in this context.

D:\Hf\Verilog\Unpacked\Src\Common>
I want value (pwr) to be successive powers of two each time I go through 
one iteration of the loop. Can anyone tell me why this code doesn't work 
and/or what I need to do to fix it? Thanks in advance for any 
suggestions you can give me.

von Klakx (Guest)


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I think the error is more important.

Try this
localparam integer  bases [ nmLevels:0];

von Kevin S. (kvnsmnsn)


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Klakx: "I think the error is more important. Try this localparam integer 
bases [ nmLevels:0];" I'm fine with fixing the error before dealing with 
the warning. But I
made the change you suggested:
module expLif ();
parameter  integer nmBits  = 1;
localparam integer highBit = nmBits - 1;
output             lssThn;
input [ highBit:0] leftOp;
input [ highBit:0] rightOp;

typedef enum { CORNER, E_LEAF, N_LEAF, SIDE, E_INTERIOR, N_INTERIOR } nodeType;
typedef struct packed
{ nodeType ndType;
   integer inLow;
   integer inHigh;
   integer out;
} node;

localparam integer nmNodes  = 2 * nmBits - 1;
localparam integer nmLevels = $clog2( nmBits) + 1;

localparam integer bases [ nmLevels:0];

initial

begin
  integer lvl;
  integer pwr = 1;
  bases[ 0]   = 1;
  for (lvl = 1; lvl <= nmLevels; lvl = lvl + 1)
  begin
    bases[ lvl] = bases[ lvl - 1] + ((nmNodes + pwr >> lvl << 1) - 1);
    pwr       <<= 1;
  end
end

endmodule
and then when I used Icarus to attempt to simulate it I got:
E:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o expLif.vvp expLif.sv
expLif.sv:19: syntax error
expLif.sv:19: error: syntax error localparam list.
expLif.sv:25: warning: Static variable initialization requires explicit lifetime in this context.

E:\Hf\Verilog\Unpacked\Src\Common>
so the change you suggested doesn't appear to have fixed the error. Do 
you have any other ideas on what might be causing the error and/or how I 
can fix it? Anybody know what I'm doing wrong here?

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