EmbDev.net

Forum: FPGA, VHDL & Verilog Error in Loading Design


von NAZMUL HASAN (Guest)


Attached files:

Rate this post
0 useful
not useful
Error messages show: [ModelSim PE Student 10.4a] kind help is 
appreciated

# vsim -gui
# Start time: 22:41:25 on Sep 10,2020
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.aac2m1p1_tb(behavioral)
# ** Error: (vsim-3173) Entity 
'C:/Modeltech_pe_edu_10.4a/CE-VErilogFpga/work.comparator2' has no 
architecture.
#
# Load interrupted
# Error loading design

von -gb- (Guest)


Rate this post
0 useful
not useful
Your comparator2 has no architecture description.

Post your code for more help.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig