Forum: FPGA, VHDL & Verilog Error in Loading Design

von NAZMUL HASAN (Guest)

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Error messages show: [ModelSim PE Student 10.4a] kind help is 

# vsim -gui
# Start time: 22:41:25 on Sep 10,2020
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.aac2m1p1_tb(behavioral)
# ** Error: (vsim-3173) Entity 
'C:/Modeltech_pe_edu_10.4a/CE-VErilogFpga/work.comparator2' has no 
# Load interrupted
# Error loading design

von -gb- (Guest)

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Your comparator2 has no architecture description.

Post your code for more help.


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