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Forum: FPGA, VHDL & Verilog Can anyone explain "cannot currently create a parameter of type" compilation error message?


von Kevin S. (kvnsmnsn)


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I've written a piece of code with inputs (left) and (right) and output 
(result), each of which operand is a single bit, which returns a logical 
one in (result) if (left) has the same value as (right), and returns a 
logical zero otherwise. My code is:
module ModGc ( result, left, right);
output result;
input  left, right;

typedef enum { L_NOT, L_NAND, L_NOR } GateType;

typedef struct packed
{ GateType gateTp;
   integer out;
   integer inLow;
   integer inHigh;
} LogGate;

localparam integer nmGates  = 4;
localparam integer poolSize = 6;
localparam LogGate specs [ nmGates:1]
wire               pool  [ poolSize:1];
genvar             ix;

initial
begin
  specs[ 1].gateTp = L_NOR ; specs[ 1].out = 4; specs[ 1].inLow = 2; specs[ 1].inHigh = 3;
  specs[ 2].gateTp = L_NOT ; specs[ 2].out = 5; specs[ 2].inLow = 4; specs[ 2].inHigh = 0;
  specs[ 3].gateTp = L_NAND; specs[ 3].out = 6; specs[ 3].inLow = 2; specs[ 3].inHigh = 3;
  specs[ 4].gateTp = L_NOR ; specs[ 4].out = 1; specs[ 4].inLow = 5; specs[ 4].inHigh = 6;
end
  
assign pool[ 2] = left;
assign pool[ 3] = right;
for (ix = 1; ix <= nmGates; ix = ix + 1)
  case (specs[ ix].gateTp)
    L_NOT
  : not ntx( pool[ specs[ ix].out], pool[ specs[ ix].inLow]);
    L_NAND
  : nand nax( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
    L_NOR
  : nor nox( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
  endcase
assign result = pool[ 1];

endmodule
Once again, I'm fully aware that there's a much simpler way to design an 
Equals circuit than this; again this is a simplification of a problem 
I'm having in more complex code. Anyhow, I run the Icarus simulator on 
this and get:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o ModGc.out ModGc.sv
ModGc.sv:16: sorry: cannot currently create a parameter of type 'LogGate' which was defined at: ModGc.sv:7.
ModGc.sv:16: syntax error
ModGc.sv:16: error: syntax error localparam list.

D:\Hf\Verilog\Unpacked\Common>
Can anyone tell me why the simulator is balking at line 16, where local 
parameter (specs) is declared? Any information anyone can give me on 
these compilation errors would be greatly appreciated.

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