I've written a piece of code with inputs (left) and (right) and output
(result), each of which operand is a single bit, which returns a logical
one in (result) if (left) has the same value as (right), and returns a
logical zero otherwise. My code is:
1 | module ModGc ( result, left, right);
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2 | output result;
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3 | input left, right;
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4 |
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5 | typedef enum { L_NOT, L_NAND, L_NOR } GateType;
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6 |
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7 | typedef struct packed
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8 | { GateType gateTp;
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9 | integer out;
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10 | integer inLow;
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11 | integer inHigh;
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12 | } LogGate;
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13 |
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14 | localparam integer nmGates = 4;
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15 | localparam integer poolSize = 6;
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16 | localparam LogGate specs [ nmGates:1]
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17 | wire pool [ poolSize:1];
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18 | genvar ix;
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19 |
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20 | initial
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21 | begin
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22 | specs[ 1].gateTp = L_NOR ; specs[ 1].out = 4; specs[ 1].inLow = 2; specs[ 1].inHigh = 3;
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23 | specs[ 2].gateTp = L_NOT ; specs[ 2].out = 5; specs[ 2].inLow = 4; specs[ 2].inHigh = 0;
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24 | specs[ 3].gateTp = L_NAND; specs[ 3].out = 6; specs[ 3].inLow = 2; specs[ 3].inHigh = 3;
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25 | specs[ 4].gateTp = L_NOR ; specs[ 4].out = 1; specs[ 4].inLow = 5; specs[ 4].inHigh = 6;
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26 | end
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27 |
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28 | assign pool[ 2] = left;
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29 | assign pool[ 3] = right;
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30 | for (ix = 1; ix <= nmGates; ix = ix + 1)
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31 | case (specs[ ix].gateTp)
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32 | L_NOT
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33 | : not ntx( pool[ specs[ ix].out], pool[ specs[ ix].inLow]);
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34 | L_NAND
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35 | : nand nax( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
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36 | L_NOR
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37 | : nor nox( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
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38 | endcase
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39 | assign result = pool[ 1];
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40 |
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41 | endmodule
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Once again, I'm fully aware that there's a much simpler way to design an
Equals circuit than this; again this is a simplification of a problem
I'm having in more complex code. Anyhow, I run the Icarus simulator on
this and get:
1 | D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o ModGc.out ModGc.sv
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2 | ModGc.sv:16: sorry: cannot currently create a parameter of type 'LogGate' which was defined at: ModGc.sv:7.
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3 | ModGc.sv:16: syntax error
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4 | ModGc.sv:16: error: syntax error localparam list.
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5 |
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6 | D:\Hf\Verilog\Unpacked\Common>
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Can anyone tell me why the simulator is balking at line 16, where local
parameter (specs) is declared? Any information anyone can give me on
these compilation errors would be greatly appreciated.
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