I've written a bit of Verilog code that takes two input operands 
(leftOp) and (rightOp) and outputs (result), with a parameter (nmBits) 
that is the common length of all three of those operands, set to one by 
default. My code is:

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module bwEqu ( result, leftOp, rightOp);

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parameter nmBits = 1;

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integer highBit = nmBits - 1;

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output [ highBit:0] result;

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input  [ highBit:0] leftOp;

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input  [ highBit:0] rightOp;

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integer poolSize = 3 * nmBits;

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integer highPool = poolSize - 1;

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wire pool [ highPool:0];

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genvar ix;

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for (ix = 0; ix <= highPool; ix = ix + 3)

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begin

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  nand2 na0( pool[ ix], leftOp[ ix / 3], rightOp[ ix / 3]);

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  nor2 no0( pool[ ix + 1], leftOp[ ix / 3], rightOp[ ix / 3]);

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  nt1 nt0( pool[ ix + 2], pool[ ix + 1]);

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  nor2 no1( result[ ix / 3], pool[ ix], pool[ ix + 2]);

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end

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endmodule

When I try to simulate this with Icarus I get the following error 
messages:

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D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o bwEqu.out bwEqu.sv

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bwEqu.sv:13: error: Unable to bind parameter `highPool' in `bwEqu'

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bwEqu.sv:13: error: Cannot evaluate genvar conditional expression: (ix)<=(highPool)

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2 error(s) during elaboration.

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D:\Hf\Verilog\Unpacked\Common>

Now I realize that there are much more simple ways of accomplishing my 
bit-wise equal that won't suffer from these problems; this is sort of a 
simplification of a problem I'm having with a considerably more 
complicated piece of code. The problem is the same; I've got an integer 
value, in this case (highPool), that I'm using to control my (for) loop, 
and for some reason the simulator is balking when it comes to comparing 
(ix) with that value. Anybody have any idea why Icarus is having this 
problem, and what I can do to solve the problem (short of splitting 
(pool) into three separate arrays)?