Forum: FPGA, VHDL & Verilog Is it illegal to use an (enum) as a function input?

von Kevin S. (kvnsmnsn)

Rate this post
0 useful
not useful
I'm still very much interested in finding out whether or not it's 
possible for a Verilog function to have a boolean value as input, but 
while I was waiting for input on that I decided to rewrite a version of 
my Verilog code to use an (enum) instead of a (boolean). Much to my 
amazement, it appears that I can't use an (enum) as an input to a 
function either! I wrote the following code:
module useBin ();

typedef enum { ADD, MULTIPLY } binOp;

function integer execOp;
    input integer left;
    input integer right;
    input   binOp op;
    execOp = op == ADD ? left + right : left * right;

When I ran Icarus to simulate it I got:
D:\Hf\Verilog\Unpacked\Common>ive useBin
\Icarus\bin\iverilog -g2009 -o useBin.out useBin.sv
useBin.sv:8: syntax error
useBin.sv:5: error: Syntax error defining function.

I can kind of understand why a (boolean) might cause a problem when used 
as a function input, but why in the world would it be illegal to use an 
(enum) like my (binOp) as a function input?


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig