I'm still very much interested in finding out whether or not it's 
possible for a Verilog function to have a boolean value as input, but 
while I was waiting for input on that I decided to rewrite a version of 
my Verilog code to use an (enum) instead of a (boolean). Much to my 
amazement, it appears that I can't use an (enum) as an input to a 
function either! I wrote the following code:

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module useBin ();

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typedef enum { ADD, MULTIPLY } binOp;

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function integer execOp;

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    input integer left;

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    input integer right;

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    input   binOp op;

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  begin

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    execOp = op == ADD ? left + right : left * right;

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  end

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endfunction

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endmodule

When I ran Icarus to simulate it I got:

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D:\Hf\Verilog\Unpacked\Common>ive useBin

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\Icarus\bin\iverilog -g2009 -o useBin.out useBin.sv

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useBin.sv:8: syntax error

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useBin.sv:5: error: Syntax error defining function.

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D:\Hf\Verilog\Unpacked\Common>

I can kind of understand why a (boolean) might cause a problem when used 
as a function input, but why in the world would it be illegal to use an 
(enum) like my (binOp) as a function input?