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Forum: FPGA, VHDL & Verilog Having trouble understanding warnings and syntax errors in my Verilog.


von Kevin S. (kvnsmnsn)


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I just got done writing a module that takes as input (operand) whose 
length varies depending on parameter (nmBits), and outputs a single bit 
(result) that I want to be the exclusive or of all the bits in 
(operand). Here's my code:
// (c) Kevin Simonson 2020

module incPort ( result, operand);
parameter nmBits = 2;
output result;
input  operand [ nmBits:1];

wire [ nmBits:2] rships;
genvar integer ix;

xor x2( rships[ 2], operand[ 1], operand[ 2]);
generate
  for (ix = 3; ix <= nmBits; ix++)
  begin
    xor xix( rships[ ix], operand[ ix], rships[ ix - 1]);
  end
endgenerate
assign result = rships[ nmBits];

endmodule
Then when I tried to simulate it with Icarus I got error messages:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o incPort.out incPort.sv
incPort.sv:6: warning: Array dimensions in incomplete port declarations are currently ignored.
incPort.sv:6:        : The dimensions specified in the net or variable declaration will be used.
incPort.sv:9: syntax error
incPort.sv:9: error: invalid module item.
incPort.sv:13: syntax error
incPort.sv:15: error: invalid module item.
incPort.sv:16: syntax error
incPort.sv:18: error: invalid module item.
incPort.sv:20: syntax error
I give up.

D:\Hf\Verilog\Unpacked\Common>
What exactly do the complaints about line 6 (line "input operand [ 
nmBits:1];") mean? And why is it calling my (genvar) declaration a 
syntax error? Furthermore, why are the beginning of my for loop, the 
(end) at the end of that for loop, and the (endmodule) declaration 
designated as syntax errors? Any information on this would be greatly 
appreciated.

von Andy (Guest)


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> input  operand [ nmBits:1];
 Die Bitweite muss vor dem Namen stehen (wie bei wire)

> genvar integer ix;
 Lass integer weg.

> xor x2( rships[ 2], operand[ 1], operand[ 2]);
 Der operator für XOR ist ^

>   for (ix = 3; ix <= nmBits; ix++)
 ix++ geht nicht in Verilog, schreibe ix=ix+1


Hier eine sehr vereinfachte Version:
module incPort ( result, operand);
 parameter nmBits = 2;
 output result;
 input  [nmBits-1:0] operand;

 assign result = ^operand;

endmodule

von Andy (Guest)


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Sorry just realized this is from the english forum

> input  operand [ nmBits:1];
 write the bitsize before the label, like you've done for wire

> genvar integer ix;
 No 'integer' needed

> xor x2( rships[ 2], operand[ 1], operand[ 2]);
 Use ^ for xor, like in C.

>   for (ix = 3; ix <= nmBits; ix++)
 ix++ is no valid Verilog, use: ix=ix+1


A simplified version of your module:
module incPort (result, operand);
 parameter nmBits = 2;
 output result;
 input  [nmBits-1:0] operand;

 assign result = ^operand;

endmodule

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