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Forum: FPGA, VHDL & Verilog How do I declare a packed array in Verilog?


von Kevin S. (kvnsmnsn)


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I've created an (enum) called (color), and included it in a packed 
(struct) called (triple), and then created a ten-element array called 
(group) in the following code:
module EnStAr ();

typedef enum { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET } color;
typedef struct packed
{   color clr;
  integer xCoo;
  integer yCoo;
} triple;

triple [ 9:0] group;

endmodule
When I execute the following command I get the following single error 
message:
D:\Hf\Verilog\Common>\Icarus\bin\iverilog -g2009 -o EnStAr.out EnStAr.sv
EnStAr.sv:10: Compound type is not PACKED in this context.

D:\Hf\Verilog\Common>
Line 10 is where I declare my array. Is this saying my array is not 
packed? If so, how do I fix this so that my array is packed? I guess the 
bottom line is, how do I change this file so that Icarus' simulator will 
compile it without error messages?

von Vancouver (Guest)


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Could you solve the Problem? Your code compiles w/o problems in Questa. 
Maybe icarus cannot deal with packed arrays of complex elements. Do you 
really need a packed array here? Otherwise try
triple group [9:0]

von Kevin S. (kvnsmnsn)


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Vancouver: "Do you really need a packed array here? Otherwise try / 
triple group [9:0]". I tried that and it compiled without any complaint 
at all. Thanks! So I have to pack my (struct), but having done that I 
can't pack an array of that (struct)? Why is that?

von Vancouver (Guest)


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To be honest, I dont know. Generally it is supported by SV, but it seems 
Icarus does not.
Anyway, a packed array only makes sense if you want to assign the 
complete array from a large bit vector for example. In this case, the 
array must be "dense", as the bit vector is. If the array elements are 
addressed via array index only, there is no need for using packed 
arrays.

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