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Forum: FPGA, VHDL & Verilog Cannot get icarus to recognize enum or struct.


von Kevin S. (kvnsmnsn)


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I copied the following section of code:
// https://www.chipverify.com/systemverilog/systemverilog-enumeration

module tb;
  // "e_true_false" is a new data-type with two valid values: TRUE and FALSE
  typedef enum {TRUE, FALSE} e_true_false;

  initial begin
    // Declare a variable of type "e_true_false" that can store TRUE or FALSE
    e_true_false  answer;

    // Assign TRUE/FALSE to the enumerated variable
    answer = TRUE;

    // Display string value of the variable
    $display ("answer = %s", answer.name);
  end
endmodule
verbatim from 
"https://www.chipverify.com/systemverilog/systemverilog-enumeration";, 
fourth code listing, except I added that initial comment and a blank 
line. I'm currently using Icarus as my tool to simulate Verilog. When I 
execute the following:
D:\Hf\Verilog\Common>\Icarus\bin\iverilog tb.sv
tb.sv:5: syntax error
tb.sv:5: error: Invalid module instantiation
tb.sv:9: syntax error
tb.sv:9: error: malformed statement

D:\Hf\Verilog\Common>
I get those error messages. It would appear Icarus can't handle 
enumerations. In addition to not being able to use enumerations in 
Verilog with Icarus, it looks like I cannot use a struct either. My code 
uses the example from 
"http://www.testbench.in/SV_07_STRUCTURES_AND_UNIOUNS.html"; like so:
module Se;

struct packed {
integer a;
byte b;
bit[0:7] c;
} my_data;

my_data.b = 8'b10;
$display( "%d", my_data.a);

endmodule
This example is precisely the example on that page, sandwiched between a 
"module Se;" and an "endmodule". When I execute my simulator on it I 
get:
D:\Hf\Verilog\Common>\Icarus\bin\iverilog Se.sv
Se.sv:3: syntax error
Se.sv:3: error: Invalid module instantiation
Se.sv:5: syntax error
Se.sv:5: error: Invalid module instantiation
Se.sv:6: error: Invalid module instantiation
Se.sv:7: error: invalid module item.
Se.sv:9: syntax error
Se.sv:9: error: Invalid module instantiation
Se.sv:10: error: invalid module item.

D:\Hf\Verilog\Common>
What do I have to do to get Icarus to recognize enums and/or structs? Or 
if I can't do it with Icarus, is there a free simulator that does 
recognize enums and structs?

von Klakx (Guest)


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Use flag -g2009 to enable sv

von Kevin S (Guest)


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Okay, that fixed the biggest problem I had with enumerations. But I'm 
still having trouble getting structs to work. I modified "Se.sv" like 
follows:
module Se;

typedef struct packed {
integer a;
byte b;
bit[0:7] c;
} my_data;

my_data md;
md.b = 8'b10;
$display( "md.a: %d, md.b: %d", md.a, md.b);

endmodule
Then I executed my Icarus simulator and got the following error 
messages:
D:\Hf\Verilog\Common>\Icarus\bin\iverilog -g2009 Se.sv
Se.sv:10: syntax error
Se.sv:10: error: Invalid module instantiation
Se.sv:11: error: invalid module item.

D:\Hf\Verilog\Common>
Line 10 is the line that says, "md.b = 8'b10;". Does anyone know what 
the syntax error is my simulator is talking about? And what's wrong with 
the instantiation on that line? And why is it complaining about an 
"Invalid module item" on the next line?

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