AS Alexander S. (alex_isr) OP (Company: Home) 2020-06-12 22:39 #6300758 Rate this post • ▲ useful ▼ not useful Attached ModelSim VHDL design of Generic Decoder with Rise OutPut. Regards Alex. Attached files: DecoderDigDef_InxOut.zip (105 KB) DecoderDigDef_InxOut.PNG (72 KB) Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post