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Forum: FPGA, VHDL & Verilog Left and right nibble from unsigned


von Tarik (Guest)


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Hello guys im new here so pardon me if i made some mistakes in making 
this post.

I'm doing my assignment and I need to find left and right nibble of 
unsigned signal.

signal wdata:unsigned (7 down to 0);
This is the signal from i need to take left and right nibble.So how 
should i do it should i declare two unsigned signals with 4 bits and 
trie to slice the wdata or something else.Thank you in advance.

:
von Achim S. (Guest)


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wdata(7 downto 4) is the left nibble. you can assign it to another 
signal or handle it however you want.

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