I am working on verilog project in lattice diamond. I synthesize and compile correctly my code. I write my lpf (constraints file) to place pins,but when i try to visualize the pin/port assignment in the spreadsheet view ,i get these errors: ERROR - The port [clk_ch1_p_i] doesn't exist in the design. ERROR - The port [d0_ch1_p_i] doesn't exist in the design. ERROR - The port [d1_ch1_p_i] doesn't exist in the design. However these signals exist in my design and are declared in the top module. please could someone help me.
Probably these ports are never used or in case they are used, the signals that these ports have impact on are never assigned to output pins. Then the systhesis throws them away. Have a look in your synthesis report to find out.
Are there more errors of this kind or just on these signals? Is this the toplevel of your design? If not, check whether you accidentally tied reset_n_i constantly active somewhere outside the module. This would remove some clocked logic from your design and thus make clock signal obsolete. Is the component configured to use single ended clock instead of differential one? And why are all ports declared as inout?