Hello, I implemented Tracking ADC in FPGA. ADC board is interfaced with FPGA. For Vadj=1.8V, the sine wave generated from signal generator can be reconstructed/represented in ila core for a maximum amplitude of 870mV and offset of 440mV. For Vadj=3.3V, the sine wave generated from signal generator can be reconstructed in ila core for a maximum amplitude of 1.08V and offset of 560mV. 1)For Vadj=1.8V, the max output code of ADC is 253 and for Vadj=3.3V, the max output code of ADC is 174. What's the reason for decrease in quantization levels? 2) How the Vadj(1.8,3.3) and sinewave amplitudes(870mV, 1.08V) are related?
Guest
#6109895
Is the ADC in the FPGA? XADC? Which exact ADC are you using and on which Board?
I’m using Tracking ADC external board. Tracking ADC has three components:Comparator, counter and DAC. PCB board has comparator and DAc. Counter is implemented in FPGA and interface with eternal board.
Guest
#6109910
OK, so ... do you habe an Schematic? Please post it. I habe no clue where vadj is. And please describe the generator signal. Amplitude and DC offset. And Name the DAC.