You probably describe the state machine inside a clocked process. Then
an unassigned signal just keeps its value. If you go to state m from
state n, b will still be '0'.
If you want to define a default value, assign the value at the beginning
of the process. In a process only the last assigned value is assigned to
wait until rising_edge(clk);
case state is
when n =>
when m =>
When state is n, b will be '0', when state is m, b will be '1', because
'1' is assigned to b and it is not overwritten later.
Just for clarification:
'a' will always be '0'. It will not toggle. Only the last assignment