You probably describe the state machine inside a clocked process. Then
an unassigned signal just keeps its value. If you go to state m from
state n, b will still be '0'.
If you want to define a default value, assign the value at the beginning
of the process. In a process only the last assigned value is assigned to
a signal.
1 | process(clk) begin
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2 | wait until rising_edge(clk);
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3 | a<='0';
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4 | b<='1';
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5 | case state is
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6 | when n =>
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7 | a<='1';
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8 | b<='0';
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9 | when m =>
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10 | a<='1';
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11 | end case;
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12 | end process;
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When state is n, b will be '0', when state is m, b will be '1', because
'1' is assigned to b and it is not overwritten later.
Just for clarification:
1 | process begin
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2 | a<='1';
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3 | a<='0';
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4 | a<='1';
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5 | a<='0';
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6 | end process;
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'a' will always be '0'. It will not toggle. Only the last assignment
is executed.