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Forum: FPGA, VHDL & Verilog FSM problems


von maurizio stefani (Guest)


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HI,
during the development of FSM sometimes I forget to declare the status 
of variable (i.e. std_logic). Just as example:
- state n: a<='1'; b<='0';
- state m: a<='0';
in the state m "b" is not declared and then it could assume any value.

Is there a way to chose the default value for a signal, in this way if I 
forget to set it in a state the value will be assumed as specified 
default?
thank you
maurizio stefani

von Dussel (Guest)


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You probably describe the state machine inside a clocked process. Then 
an unassigned signal just keeps its value. If you go to state m from 
state n, b will still be '0'.

If you want to define a default value, assign the value at the beginning 
of the process. In a process only the last assigned value is assigned to 
a signal.
process(clk) begin
  wait until rising_edge(clk);
  a<='0';
  b<='1';
  case state is
    when n =>
      a<='1';
      b<='0';
    when m =>
      a<='1';
  end case;
end process;

When state is n, b will be '0', when state is m, b will be '1', because 
'1' is assigned to b and it is not overwritten later.

Just for clarification:
process begin
  a<='1';
  a<='0';
  a<='1';
  a<='0';
end process;
'a' will always be '0'. It will not toggle. Only the last assignment 
is executed.

von Maurizio S. (Company: progsel) (maurizio)


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HI,
thank you for your help, I will check asap

maurizio stefani

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