EmbDev.net

Forum: FPGA, VHDL & Verilog Sha 3, Output Reading Input with delay


Sha 3, Output Reading Input with delay
von Elena S. (elena98)

Rate this post
0 ▲ useful
▼ not useful 
I am working on my thesis and i have problem with it.

Output Reading Input with delay
Can anyone Help me?

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig