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Forum: FPGA, VHDL & Verilog DE2-115 FPGA Verilog blink LED based on counter


von Trung B. (chichoichoi)


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Hello,
I am using DE2-115 FPGA to make LEDG[0] and LEDG[1] blink respectively.
LEDG[0] will be on in 2s. In that period of time, LEDG[1] will be off.
After that, LEDG[0] will be off and LEDG[1] will be on for 2 seconds.
In the end, I have reset line to make the blink test repeat again.
The clock is 50Mhz => 2s is 10^8 period = 9'd100000000.
After I connected with the FPGA and run the code, the LEDG[8] was on but 
the LEDG[0] was on forever and the LEDG[1] was off forever as well.
Please help me!
Thank you



module GD (
    input CLOCK_50,
    output [8:0] LEDG
);

    reg [31:0] counter = 0;
    reg reset = 1;

    assign LEDG[7:0] = 1’b0;
    assign LEDG[8] = 1’b1;
    /* always */
   always @ (posedge CLOCK_50) begin
    if (reset==0)
      counter <= 0;
    else
      counter <= counter + 1;
    end
    always @ (posedge CLOCK_50) begin
        if (counter < 9'd100000000 ) begin
          LEDG[0] <= 1'b1;
          LEDG[1] <= 1'b0;
        end else begin
          if (counter < 9'd200000000 ) begin
          LEDG[0] <= 1'b0;
          LEDG[1] <= 1'b1;
          end else
          reset <= 0;
          end

        end

endmodule

von Andy (Guest)


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I don't think your code syntesize without errors. In an always block, 
you can only write into registers, but your LEDGs are wires.

So you need a register for the LED states and assign that to the 
outputs:
module GD (
    input CLOCK_50,
    output [8:0] LEDG
);

    reg [31:0] counter = 0;
    reg reset = 1'b1;
    reg ledState = 1'b0;

    assign LEDG[7:0] =  ledState;
    assign LEDG[8]   = ~ledState;

    always @ (posedge CLOCK_50) begin
       if (reset==0)
          counter <= 0;
       else
          counter <= counter + 1;

       if (counter == 99_999_999 ) begin
          ledState <= ~ledState;
          counter  <= 0;
       end
    end

endmodule

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