The Verilog module I want to write has a parameter that is an integer, and I need to create an array of integers whose length is the ceiling of (smallest integer greater than or equal to) the log (base two) of that parameter. Does anyone know how I can do that in Verilog?
So why not simply writing a log_2() function in verilog and use this in the declaration of the integer array? There are plenty examples for doing so, e.g. https://www.edaboard.com/showthread.php?177879-how-to-calculate-log2(n)-in-verilog