Forum: FPGA, VHDL & Verilog How can I make array length the logarithm of an input parameter in Verilog?

von Kevin S. (kvnsmnsn)

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The Verilog module I want to write has a parameter that is an integer, 
and I need to create an array of integers whose length is the ceiling of 
(smallest integer greater than or equal to) the log (base two) of that 
parameter. Does anyone know how I can do that in Verilog?

von Vancouver (Guest)

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So why not simply writing a log_2() function in verilog and use this in 
the declaration of the integer array? There are plenty examples for 
doing so,


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