Can size of a port be input as a parameter?

Kevin S. OP #5991541
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I have a hardware algorithm that compares two operands, each (keyBits) 
bits long, and returns a logical one if the first operand is less than 
the second, and returns a logical zero otherwise. This algorithm works 
for any integer value of (keyBits) greater than one. So can I write my 
algorithm with the following Verilog code, by passing (keyBits) in as a 
parameter? I haven't tried compiling or simulating this code; quite 
frankly I don't know how to do either. Can anyone help me with that?

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module lessThan ( lfLessThanRg, left, right);

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parameter integer keyBits = 2;

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integer maxBit = keyBits - 1;

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output lfLessThanRg;

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input [maxBit:0] left, right;

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wire[maxBit:0] notLeft;

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wire[maxBit:1] ltHere, ltEve, ltBelow, equal;

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or( lfLessThanRg, ltHere[ maxBit], ltEve[ maxBit]);

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genvar integer bit;

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generate

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  for (bit = maxBit; 0 < bit; bit = bit - 1)

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  begin

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    and( ltHere[ bit], notLeft[ bit], right[ bit]);

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    and( ltEve[ bit], equal[ bit], ltBelow[ bit]);

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    or( equal[ bit], notLeft[ bit], right[ bit]);

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    not( notLeft[ bit], left[ bit]);

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    if (1 < bit)

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    begin

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      or( ltBelow[ bit], ltHere[ bit - 1], ltEve[ bit - 1]);

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    end

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  end

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endgenerate

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and( ltBelow[ 1], notLeft[ 0], right[ 0]);

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not( notLeft[ 0], left[ 0]);

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endmodule
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Andy Guest #5991673
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Why can you not just write it like that:

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module lessThan ( lfLessThanRg, left, right);

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parameter keyBits = 2;

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output lfLessThanRg;

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input [keyBits-1:0] left, right;

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assign lfLessThanRg = left < right;

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endmodule


How you compile or simulate depends alot on the tools you use. I would 
try  icarus verilog. I'm pretty sure you can find several tutorials in 
the web for it.
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