# Forum: FPGA, VHDL & Verilog Can size of a port be input as a parameter?

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I have a hardware algorithm that compares two operands, each (keyBits)
bits long, and returns a logical one if the first operand is less than
the second, and returns a logical zero otherwise. This algorithm works
for any integer value of (keyBits) greater than one. So can I write my
algorithm with the following Verilog code, by passing (keyBits) in as a
parameter? I haven't tried compiling or simulating this code; quite
frankly I don't know how to do either. Can anyone help me with that?

 module lessThan ( lfLessThanRg, left, right); parameter integer keyBits = 2; integer maxBit = keyBits - 1; output lfLessThanRg; input [maxBit:0] left, right; wire[maxBit:0] notLeft; wire[maxBit:1] ltHere, ltEve, ltBelow, equal; or( lfLessThanRg, ltHere[ maxBit], ltEve[ maxBit]); genvar integer bit; generate for (bit = maxBit; 0 < bit; bit = bit - 1) begin and( ltHere[ bit], notLeft[ bit], right[ bit]); and( ltEve[ bit], equal[ bit], ltBelow[ bit]); or( equal[ bit], notLeft[ bit], right[ bit]); not( notLeft[ bit], left[ bit]); if (1 < bit) begin or( ltBelow[ bit], ltHere[ bit - 1], ltEve[ bit - 1]); end end endgenerate and( ltBelow[ 1], notLeft[ 0], right[ 0]); not( notLeft[ 0], left[ 0]); endmodule 

: Edited by User

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Why can you not just write it like that:

 module lessThan ( lfLessThanRg, left, right); parameter keyBits = 2; output lfLessThanRg; input [keyBits-1:0] left, right; assign lfLessThanRg = left < right; endmodule 

How you compile or simulate depends alot on the tools you use. I would
try  icarus verilog. I'm pretty sure you can find several tutorials in
the web for it.

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