I have a hardware algorithm that compares two operands, each (keyBits)
bits long, and returns a logical one if the first operand is less than
the second, and returns a logical zero otherwise. This algorithm works
for any integer value of (keyBits) greater than one. So can I write my
algorithm with the following Verilog code, by passing (keyBits) in as a
parameter? I haven't tried compiling or simulating this code; quite
frankly I don't know how to do either. Can anyone help me with that?
1 | module lessThan ( lfLessThanRg, left, right);
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2 |
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3 | parameter integer keyBits = 2;
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4 | integer maxBit = keyBits - 1;
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5 |
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6 | output lfLessThanRg;
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7 | input [maxBit:0] left, right;
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8 |
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9 | wire[maxBit:0] notLeft;
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10 | wire[maxBit:1] ltHere, ltEve, ltBelow, equal;
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11 |
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12 | or( lfLessThanRg, ltHere[ maxBit], ltEve[ maxBit]);
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13 |
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14 | genvar integer bit;
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15 |
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16 | generate
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17 | for (bit = maxBit; 0 < bit; bit = bit - 1)
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18 | begin
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19 | and( ltHere[ bit], notLeft[ bit], right[ bit]);
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20 | and( ltEve[ bit], equal[ bit], ltBelow[ bit]);
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21 | or( equal[ bit], notLeft[ bit], right[ bit]);
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22 | not( notLeft[ bit], left[ bit]);
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23 | if (1 < bit)
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24 | begin
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25 | or( ltBelow[ bit], ltHere[ bit - 1], ltEve[ bit - 1]);
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26 | end
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27 | end
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28 | endgenerate
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29 |
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30 | and( ltBelow[ 1], notLeft[ 0], right[ 0]);
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31 | not( notLeft[ 0], left[ 0]);
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32 |
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33 | endmodule
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