Usually you would provide an interface to the flash PROM from your FPGA 
and handle the programming of the flash with a simple interface to the 
FPGA:

- erase flash command
- write byte/block command
- optional: read byte/block command for verify

So you just send the erase and then program the bytes(if slow is no 
problem) or blocks with sequential writes, when the last write is done.

If you already have a RS485 connection from a PC to your FPGA this is 
not too difficult.

Just make sure, when designing the PCB, that you have the correct pins 
connected between FPGA and flash.

Some interfaces are bidrectional: you can use the pins for configuration 
of the FPGA and later on read/write the flash from the FPGA. But that 
differs from one FPGA/Flash to another.

If an Altera/Intel is also possible, there is a wonderfully simple 
possibility: 
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altremote.pdf

Almost as godlike as Trump.

Check for the XTP059 appnote at Xilinx, this also works for Kintex. 
However I am only aware of Ethernet based solution, not RS485

Hi,

I've got a solution implemented on the Xilinx Spartan6 using the ICAP 
primitive, however it's Ethernet based. It simply acts as a bootloader 
('golden' image) which will look for a valid image in the 'alternate 
bootstrap' flash area. That image can be written over Ethernet, likewise 
it would work on any other interface, it's just a matter of the 
protocol.
I've got some basic LabVIEW support going, but haven't tested in system 
upgrade in particular.
I'd strongly recommend a setup which features a CPU core. And: it's easy 
to lock yourself out.