I am working on a test bench process to simulate response from an ADC 
connected to my FPGA.  I am having an issue with response from a 
testbench process.

Sorry for sounding like a newby, but I thought processes continued 
forever until the simulation stops.

The process response is fine during the first ADC data generation, but 
it stops responding on the second process ADC data generation.  The 
first wait condition is satisfied.  The second wait condition is 
satified when adc_convst_1 goes low.

Here is the process that is not responding correctly.

adc_process_1 : process
begin
  --L1: loop
    --if (end_Test = '0') then
      wait until (adc_cs_1 = '0' and adc_stby_1 = '1');

      wait until (adc_convst_1 = '0');
        wait for T6;
        wait for Tconv;
        adc_eoc_1 <= '0';
        wait for T7;
        adc_eoc_1 <= '1';

      wait until (adc_rd_1 = '0');
        wait for T9;
        data_bus_sig <= data_bus_sig + x"010";
    -- else
      -- exit L1;
    -- end if;
  --end loop;

I was initially thought the process needed a loop statement, but that 
didn't see to help.

I attached the full testbench file and a picture of the simulation 
results.

If you see anything I am doing wrong please let me know.

Thanks
Joe