Forum: FPGA, VHDL & Verilog VHDL Testbench Process Issue

von Josef F. (Company: Baker Hughes a GE Company) (fpgas_again)

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I am working on a test bench process to simulate response from an ADC 
connected to my FPGA.  I am having an issue with response from a 
testbench process.

Sorry for sounding like a newby, but I thought processes continued 
forever until the simulation stops.

The process response is fine during the first ADC data generation, but 
it stops responding on the second process ADC data generation.  The 
first wait condition is satisfied.  The second wait condition is 
satified when adc_convst_1 goes low.

Here is the process that is not responding correctly.

adc_process_1 : process
  --L1: loop
    --if (end_Test = '0') then
      wait until (adc_cs_1 = '0' and adc_stby_1 = '1');

      wait until (adc_convst_1 = '0');
        wait for T6;
        wait for Tconv;
        adc_eoc_1 <= '0';
        wait for T7;
        adc_eoc_1 <= '1';

      wait until (adc_rd_1 = '0');
        wait for T9;
        data_bus_sig <= data_bus_sig + x"010";
    -- else
      -- exit L1;
    -- end if;
  --end loop;

I was initially thought the process needed a loop statement, but that 
didn't see to help.

I attached the full testbench file and a picture of the simulation 

If you see anything I am doing wrong please let me know.


von Mark P. (mphil)

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The "wait until" form suspends a process until a change occurs on one or 
more of the signals in the statement and the condition is evaluated to 
be true.

(adc_cs_1 = '0' and adc_stby_1 = '1') don't change.

So do some check before "wait until" like
if (adc_cs_1 = '1') or (adc_stby_1 = '0') then

von Josef F. (Company: Baker Hughes a GE Company) (fpgas_again)

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Thanks for the help getting past that issue, but unfortunately there is 
another issue.

I didn't mention that there were two ADCs that I have to drive with this 
simulation.  I have put two ADCs in one process and seperated them with 
an if then else statement.  I did this because it appeared that there 
was an issue driving data_bus_sig with two seperate processes.  I also 
combined the conditions for driving data_bus to be activated by either 
of the ADC's cs or rd signals.

I have attached the latest test bench file and new waveform picture.


: Edited by User
von Josef F. (Company: Baker Hughes a GE Company) (fpgas_again)

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Couldn't edit last reply to include picture.

von FPGA zum Spass (Guest)

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data_bus_sig cannot be driven from 2 processes.

Do you have a single input for both ADC or two inputs?

Also, please do some newbie tutorials...the code looks awful.
- useless/dangerous libraries
- indention
- so many different processes, some work on the same thing, others don't

I hope this is for a hobby project, but i fear that it's for your job...


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