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Forum: FPGA, VHDL & Verilog Keypad saved shifting display in Verilog


von Cm Y. (cmyang)


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I'm designing a number exchange module, and so far I've been able to 
make it display on Seven Segment Display (S-S-D), like if I press 0 it 
shows 0... etc. I'm using 2 sets of 4-bits S-S-D (Common Anode).

Now I want to do like:

    default states : 0000_0000
    Now if I press 1 : 0000_0001
    If I press 2 : 0000_0012
    etc.

Whichever key I press, the display will not erase the already displaying 
number, it will shift it to the left...

And when all 8 S-S-D is full of displaying numbers like: 486C_8763, at 
this moment, when I press a key enter a number, like 1 it should be like 
: 86C8_7631; it should keep shifting to the left.

Here's my attempted code, and only been able to display it on S-S-D, and 
display all S-S-D 0000_0000... still not able to do what's been describe 
above...
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  module keydata 
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    (
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      input clk, //input clk 50MHz
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      output reg [3:0]keyout=4'b1110, //Default scan value 4bits 
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      input [3:0]keyin, //Keypad receive value
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      output reg [7:0]SegOut, //Seven Segment Display output
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      output reg [15:0]scano //Seven Segment Display Scans
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    );
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    integer z1=0,zz=0; //Registers for frequency dividing
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    reg dclk; //Divided frequency clock
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    reg [7:0]bcdz; //register for saving keypad's number value
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    reg [3:0]scan; //scan states 
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    always@(posedge clk)
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    begin
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    //---------------------
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    if(z1==50000)   //frequency divider 
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        begin
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        z1<=0;
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        scan<={scan[2:0],scan[3]}; //scanning pattern shifting resgister
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        keyout<={keyout[2:0],keyout[3]};  
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           //keypad column scanning 1110->1101->1011->0111->1110(loop)
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        end
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    else
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        z1<=z1+1;
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    //---------------------
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    //---------------------
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    if(zz==10000) //frequency divider for scanning
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        begin
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        zz<=0;
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        dclk<=~dclk;
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        end
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    else
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        zz<=zz+1;
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    //--------------------- 
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    end
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    always@(posedge dclk)  //Seven Segment Scanning
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        begin
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            case(scan)
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                    0: scano<=scano[3:0];
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                    1: scano<=scano[7:4];
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                    2: scano<=scano[11:8];
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                    3: scano<=scano[15:12];
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            endcase
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        end
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    always@(posedge dclk) //4x4 Keypad detecting 
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    begin
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        if (keyout==4'b1110) //Detecting which keyout is currently at scanning
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            begin
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            if(keyin==4'b0111) //Tell which key it is
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                begin
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                bcdz<=4'b1100;//C //the key's value,save by a register
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                end
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            else if(keyin==4'b1011)
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                begin
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                bcdz<=4'b1101; //D
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                end
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            else if(keyin==4'b1101)
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                begin
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                bcdz<=4'b1110; //E
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                end
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            else if(keyin==4'b1110)
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                begin
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                bcdz<=4'b1111;//F
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                end
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            end
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        else if (keyout==4'b1101) //Using **else if** to differentiate priorities.
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            begin
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            if(keyin==4'b0111)
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                begin
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                bcdz<=4'b1000; //8
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                end
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            else if(keyin==4'b1011)
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                begin
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                bcdz<=4'b1001; //9
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                end
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            else if(keyin==4'b1101)
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                begin
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                bcdz<=4'b1010; //A
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                end
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            else if(keyin==4'b1110)
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                begin
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                bcdz<=4'b1011; //B
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                end
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            end
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        else if (keyout==4'b1011) //4 scanning possibilities
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            begin
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            if(keyin==4'b0111)
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                begin
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                bcdz<=4'b0100; //4
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                end
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            else if(keyin==4'b1011)
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                begin
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                bcdz<=4'b0101; //5
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                end
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            else if(keyin==4'b1101)
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                begin
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                bcdz<=4'b0110; //6
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                end
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            else if(keyin==4'b1110)
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                begin
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                bcdz<=4'b0111; //7
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                end
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            end
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        else if (keyout==4'b0111)
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            begin
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            if(keyin==4'b0111)
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                begin
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                bcdz<=4'b0000; //0
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                end
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            else if(keyin==4'b1011)
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                begin
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                bcdz<=4'b0001; //1
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                end
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            else if(keyin==4'b1101)
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                begin
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                bcdz<=4'b0010; //2
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                end
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            else if(keyin==4'b1110)
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                begin
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                bcdz<=4'b0011; //3
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                end
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            end
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        end
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    always@(bcdz) //Seven Segment Decoder
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    begin
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      case(bcdz)
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          0  :  SegOut <=   8'hC0;
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          1  :  SegOut <=   8'hF9;
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          2  :  SegOut <=   8'hA4;
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          3  :  SegOut <=   8'hB0;
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          4  :  SegOut <=   8'h99;
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          5  :  SegOut <=   8'h92;
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          6  :  SegOut <=   8'h82;
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          7  :  SegOut <=   8'hF8;
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          8  :  SegOut <=   8'h80;
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          9  :  SegOut <=   8'h98;
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          10    :  SegOut <=   8'h88;
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          11  :  SegOut <=   8'h83;
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          12  :  SegOut <=   8'hC6;
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          13  :  SegOut <=   8'hA1;
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          14  :  SegOut <=   8'h86;
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          15    :  SegOut <=   8'h8E;
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          default  :  SegOut <= 8'hFF;
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      endcase
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    end
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    endmodule

: Edited by User

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