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Forum: FPGA, VHDL & Verilog $fwrite usage clarification


Author: Andrew M. (amiotto11)
Posted on:

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Trying to create a .csv file from my verilog testbench. The testbench is 
for a microprocessor and I can't figure out how to get any data to 
appear in the output file. The $fwrite's at the bottom are for the 
processor module only, but they have a header which includes variables 
from another module. Those columns will be filled by the variables from 
the other module, I just need help fixing my $fwrite portion so that 
actual data appears. Thanks.



`timescale 1ns / 1ps
module tb_processor();

logic reset;
logic clk;
logic [7:0] PC;
logic [7:0] alu_out;
logic [3:0] OPCODE;
logic [7:0] W_Register;
logic [7:0] A;
logic [7:0] B;
logic [15:0] IR;
integer logfile;

task apply_reset ();
    #100 reset <= 1;
    #100 reset <= 0;
endtask


initial begin
   clk = 0;
   apply_reset ();
end

// Instance Declarations
processor processor (
   .reset(reset),
   .clk(clk),
   .PC(PC),
   .alu_out(alu_out),
   .OPCODE(OPCODE),
   .W_Register(W_Register),
   .A(A),
   .B(B),
   .IR(IR)
);

always #10 clk = ~clk;

initial begin

logfile = $fopen("logfile.csv");
$fwrite(logfile, "PC, IR, OPCODE, RA, RB, RD, A, B, RF[RD]\n");
$fwrite(logfile, "%b, %b, %b, %b, %b, \n", PC, IR, OPCODE, A, B);
$fwrite(logfile, "%b, %b, %b, %b, %b, \n", PC, IR, OPCODE, A, B);
$fwrite(logfile, "%b, %b, %b, %b, %b, \n", PC, IR, OPCODE, A, B);
$fclose(logfile);
end

endmodule

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