Problem with Writing a SDRAM Controller

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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;    
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use IEEE.NUMERIC_STD.ALL;
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------------------------------------------------------------------------------------------------------------------------------------------------
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entity Writing is
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Port(  
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      --SDRAM
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      signal sclk  :  in  std_logic;
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      signal A    :  out  std_logic_vector(12 downto 0);
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      signal BA  :  out  std_logic_vector(1  downto 0);
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      signal CS  :  out  std_logic:='0';
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      signal RAS  :  out  std_logic:='1';
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      signal CAS  :  out  std_logic:='1';
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      signal WE  :  out  std_logic:='1';  
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      signal CKE  :  out  std_logic:='1';
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      signal DQ  :  out  std_logic_vector(15 downto 0);
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      signal LDQM  :  out  std_logic:='0';
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      signal UDQM  :  out  std_logic:='0';
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      --Control Signals
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      Signal command_write  :  in     std_logic;
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      Signal busy_write    :  out   std_logic:='0';
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      signal row_write    :  in      std_logic_vector(12 downto 0);
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      signal clmn_write    :  in      std_logic_vector(8  downto 0);
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      signal Bank_write    :  in     std_logic_vector(1  downto 0);
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      --Data Signal
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      signal Data_write    :  in   std_logic_vector(15 downto 0)
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  );
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end Writing;
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------------------------------------------------------------------------------------------------------------------------------------------------
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architecture Behavioral of Writing is
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------------------------------------------------------------------------------------------------------------------------------------------------
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Signal   Write_lvl   :integer:=0;      --Write Level(Steps)
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Signal   busy_flag  :std_logic:='0';
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constant Final_W_lvl:integer:=8;      --<<--<<  Final Write Level
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------------------------------------------------------------------------------------------------------------------------------------------------
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begin
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------------------------------------------------------------------------------------------------------------------------------------------------
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--busy_write<='1' when busy_flag='1' else
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--         '0';
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busy_write<= busy_flag;
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--------------------------------------------  
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Process
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  begin
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    wait until sclk='1';
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    if command_write='1' then
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      Busy_flag<=  '1';
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    elsif write_lvl>=1 and write_lvl<=Final_W_lvl then
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      Busy_flag<=  '1';
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    else
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      Busy_flag<=  '0';
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    end if;
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  end Process;            
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--------------------------------------------  
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--Write
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Process
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  begin
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    wait until sclk='1';
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      if Busy_flag='1' then
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          if write_lvl<=Final_W_lvl then
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            case write_lvl is
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              when 0 =>
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                --Activate                                      --Need 3 Clock (with Present Clock)--CKE Should Be High on Previous Clock 
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                CKE <= '1';                                      --This command of CKE is for Next Clock.
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                CS   <= '0';                                      --t_RCD Needs for Activating Bank and Row.   
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                RAS <= '0';  
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                CAS <= '1';
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                WE   <= '1';
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                A   <= row_write;    --ROW ADDRESS
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                BA   <= BAnk_write;      --BANK ADDRESS
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              when 2 Downto 1 =>
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                --Waiting
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                CKE<='1';
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                --NOP Command
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                CS    <='0';
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                RAS  <='1';
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                CAS  <='1';
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                WE    <='1';
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              when 3 =>
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                --Writing with Autoprecharge
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                --Writing One Byte Concurrent with Write Command in this Cycle.
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                CKE<= '1';
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                LDQM<='0';
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                UDQM<='0';
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                CS <= '0';
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                RAS<= '1';
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                CAS<= '0';
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                WE <= '0';
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                A(8 Downto 0)<= clmn_write;  --COLUMN ADDRESS
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                A(10)<= '1';            --AUTOPRECHARGE ENABLING
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                BA <= BAnk_write;              --BANK ADDRESS
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                DQ <= Data_write;
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              when 4 =>
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                --waiting to insure t_DPL (Data-In to Precharge Command Latency)
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                CKE<='1';
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                --NOP Command
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                CS    <='0';
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                RAS  <='1';
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                CAS  <='1';
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                WE    <='1';  
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              when 7 Downto 5 =>
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                --Waiting for Precharge of AutoPrecharge
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                CKE<='1';
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                --NOP Command
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                CS    <='0';
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                RAS  <='1';
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                CAS  <='1';
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                WE    <='1';  
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              when others =>
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                CKE<='1';
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                --NOP Command
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                CS    <='0';
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                RAS  <='1';
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                CAS  <='1';
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                WE    <='1';  
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            end case;
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            write_lvl<=write_lvl +1;
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          end if;
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      else
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          write_lvl<=0;
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      end if;
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  end Process;
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------------------------------------------------------------------------------------------------------------------------------------------------
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end Behavioral;

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