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Forum: FPGA, VHDL & Verilog Problem with Writing a SDRAM Controller


von Mehdi (Guest)


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;    
use IEEE.NUMERIC_STD.ALL;
------------------------------------------------------------------------------------------------------------------------------------------------
entity Writing is
Port(  
      --SDRAM
      signal sclk  :  in  std_logic;
      signal A    :  out  std_logic_vector(12 downto 0);
      signal BA  :  out  std_logic_vector(1  downto 0);
      signal CS  :  out  std_logic:='0';
      signal RAS  :  out  std_logic:='1';
      signal CAS  :  out  std_logic:='1';
      signal WE  :  out  std_logic:='1';  
      signal CKE  :  out  std_logic:='1';
      signal DQ  :  out  std_logic_vector(15 downto 0);
      signal LDQM  :  out  std_logic:='0';
      signal UDQM  :  out  std_logic:='0';
      --Control Signals
      Signal command_write  :  in     std_logic;
      Signal busy_write    :  out   std_logic:='0';
      signal row_write    :  in      std_logic_vector(12 downto 0);
      signal clmn_write    :  in      std_logic_vector(8  downto 0);
      signal Bank_write    :  in     std_logic_vector(1  downto 0);
      --Data Signal
      signal Data_write    :  in   std_logic_vector(15 downto 0)
  );
end Writing;
------------------------------------------------------------------------------------------------------------------------------------------------
architecture Behavioral of Writing is
------------------------------------------------------------------------------------------------------------------------------------------------
Signal   Write_lvl   :integer:=0;      --Write Level(Steps)
Signal   busy_flag  :std_logic:='0';

constant Final_W_lvl:integer:=8;      --<<--<<  Final Write Level
------------------------------------------------------------------------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------------------------------------------------------------------------
--busy_write<='1' when busy_flag='1' else
--         '0';
busy_write<= busy_flag;
--------------------------------------------  
Process
  begin
    wait until sclk='1';
    if command_write='1' then
      Busy_flag<=  '1';
    elsif write_lvl>=1 and write_lvl<=Final_W_lvl then
      Busy_flag<=  '1';
    else
      Busy_flag<=  '0';
    end if;
  end Process;            
--------------------------------------------  
--Write
Process
  begin
    wait until sclk='1';
      if Busy_flag='1' then
          if write_lvl<=Final_W_lvl then
            case write_lvl is
              when 0 =>
                --Activate                                      --Need 3 Clock (with Present Clock)--CKE Should Be High on Previous Clock 
                CKE <= '1';                                      --This command of CKE is for Next Clock.
                CS   <= '0';                                      --t_RCD Needs for Activating Bank and Row.   
                RAS <= '0';  
                CAS <= '1';
                WE   <= '1';
                A   <= row_write;    --ROW ADDRESS
                BA   <= BAnk_write;      --BANK ADDRESS
                
              when 2 Downto 1 =>
                --Waiting
                CKE<='1';
                --NOP Command
                CS    <='0';
                RAS  <='1';
                CAS  <='1';
                WE    <='1';
                
              when 3 =>
                --Writing with Autoprecharge
                --Writing One Byte Concurrent with Write Command in this Cycle.
                CKE<= '1';
                LDQM<='0';
                UDQM<='0';
                CS <= '0';
                RAS<= '1';
                CAS<= '0';
                WE <= '0';
                A(8 Downto 0)<= clmn_write;  --COLUMN ADDRESS
                A(10)<= '1';            --AUTOPRECHARGE ENABLING
                BA <= BAnk_write;              --BANK ADDRESS
                DQ <= Data_write;
                
              when 4 =>
                --waiting to insure t_DPL (Data-In to Precharge Command Latency)
                CKE<='1';
                --NOP Command
                CS    <='0';
                RAS  <='1';
                CAS  <='1';
                WE    <='1';  
              
              when 7 Downto 5 =>
                --Waiting for Precharge of AutoPrecharge
                CKE<='1';
                --NOP Command
                CS    <='0';
                RAS  <='1';
                CAS  <='1';
                WE    <='1';  
                
              when others =>
                CKE<='1';
                --NOP Command
                CS    <='0';
                RAS  <='1';
                CAS  <='1';
                WE    <='1';  
            end case;
            write_lvl<=write_lvl +1;
          end if;
      else
          write_lvl<=0;
      end if;
  end Process;
------------------------------------------------------------------------------------------------------------------------------------------------
end Behavioral;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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I can see no problem.
So, tell us: what do you expect and what do you get instead? And how do 
you see that wrong behaviour?

BTW: pls use the [vhdl] tags to wrap your code!

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