EmbDev.net

Forum: FPGA, VHDL & Verilog Problem with Writing a SDRAM Controller


Problem with Writing a SDRAM Controller
von Mehdi (Guest)

Rate this post
• ▲ useful
▼ not useful 
1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
use IEEE.STD_LOGIC_UNSIGNED.ALL;    

4
use IEEE.NUMERIC_STD.ALL;

5
------------------------------------------------------------------------------------------------------------------------------------------------

6
entity Writing is

7
Port(  

8
      --SDRAM

9
      signal sclk  :  in  std_logic;

10
      signal A    :  out  std_logic_vector(12 downto 0);

11
      signal BA  :  out  std_logic_vector(1  downto 0);

12
      signal CS  :  out  std_logic:='0';

13
      signal RAS  :  out  std_logic:='1';

14
      signal CAS  :  out  std_logic:='1';

15
      signal WE  :  out  std_logic:='1';  

16
      signal CKE  :  out  std_logic:='1';

17
      signal DQ  :  out  std_logic_vector(15 downto 0);

18
      signal LDQM  :  out  std_logic:='0';

19
      signal UDQM  :  out  std_logic:='0';

20
      --Control Signals

21
      Signal command_write  :  in     std_logic;

22
      Signal busy_write    :  out   std_logic:='0';

23
      signal row_write    :  in      std_logic_vector(12 downto 0);

24
      signal clmn_write    :  in      std_logic_vector(8  downto 0);

25
      signal Bank_write    :  in     std_logic_vector(1  downto 0);

26
      --Data Signal

27
      signal Data_write    :  in   std_logic_vector(15 downto 0)

28
  );

29
end Writing;

30
------------------------------------------------------------------------------------------------------------------------------------------------

31
architecture Behavioral of Writing is

32
------------------------------------------------------------------------------------------------------------------------------------------------

33
Signal   Write_lvl   :integer:=0;      --Write Level(Steps)

34
Signal   busy_flag  :std_logic:='0';

35
36
constant Final_W_lvl:integer:=8;      --<<--<<  Final Write Level

37
------------------------------------------------------------------------------------------------------------------------------------------------

38
begin

39
------------------------------------------------------------------------------------------------------------------------------------------------

40
--busy_write<='1' when busy_flag='1' else

41
--         '0';

42
busy_write<= busy_flag;

43
--------------------------------------------  

44
Process

45
  begin

46
    wait until sclk='1';

47
    if command_write='1' then

48
      Busy_flag<=  '1';

49
    elsif write_lvl>=1 and write_lvl<=Final_W_lvl then

50
      Busy_flag<=  '1';

51
    else

52
      Busy_flag<=  '0';

53
    end if;

54
  end Process;            

55
--------------------------------------------  

56
--Write

57
Process

58
  begin

59
    wait until sclk='1';

60
      if Busy_flag='1' then

61
          if write_lvl<=Final_W_lvl then

62
            case write_lvl is

63
              when 0 =>

64
                --Activate                                      --Need 3 Clock (with Present Clock)--CKE Should Be High on Previous Clock 

65
                CKE <= '1';                                      --This command of CKE is for Next Clock.

66
                CS   <= '0';                                      --t_RCD Needs for Activating Bank and Row.   

67
                RAS <= '0';  

68
                CAS <= '1';

69
                WE   <= '1';

70
                A   <= row_write;    --ROW ADDRESS

71
                BA   <= BAnk_write;      --BANK ADDRESS

72
                

73
              when 2 Downto 1 =>

74
                --Waiting

75
                CKE<='1';

76
                --NOP Command

77
                CS    <='0';

78
                RAS  <='1';

79
                CAS  <='1';

80
                WE    <='1';

81
                

82
              when 3 =>

83
                --Writing with Autoprecharge

84
                --Writing One Byte Concurrent with Write Command in this Cycle.

85
                CKE<= '1';

86
                LDQM<='0';

87
                UDQM<='0';

88
                CS <= '0';

89
                RAS<= '1';

90
                CAS<= '0';

91
                WE <= '0';

92
                A(8 Downto 0)<= clmn_write;  --COLUMN ADDRESS

93
                A(10)<= '1';            --AUTOPRECHARGE ENABLING

94
                BA <= BAnk_write;              --BANK ADDRESS

95
                DQ <= Data_write;

96
                

97
              when 4 =>

98
                --waiting to insure t_DPL (Data-In to Precharge Command Latency)

99
                CKE<='1';

100
                --NOP Command

101
                CS    <='0';

102
                RAS  <='1';

103
                CAS  <='1';

104
                WE    <='1';  

105
              

106
              when 7 Downto 5 =>

107
                --Waiting for Precharge of AutoPrecharge

108
                CKE<='1';

109
                --NOP Command

110
                CS    <='0';

111
                RAS  <='1';

112
                CAS  <='1';

113
                WE    <='1';  

114
                

115
              when others =>

116
                CKE<='1';

117
                --NOP Command

118
                CS    <='0';

119
                RAS  <='1';

120
                CAS  <='1';

121
                WE    <='1';  

122
            end case;

123
            write_lvl<=write_lvl +1;

124
          end if;

125
      else

126
          write_lvl<=0;

127
      end if;

128
  end Process;

129
------------------------------------------------------------------------------------------------------------------------------------------------

130
end Behavioral;


  


  



  

  
:
    Edited by Moderator
  

  


  

    Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
  







      

      



  

    Re: Problem with Writing a SDRAM Controller
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
I can see no problem.
So, tell us: what do you expect and what do you get instead? And how do 
you see that wrong behaviour?

BTW: pls use the [vhdl] tags to wrap your code!

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.