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Forum: FPGA, VHDL & Verilog BITSLIP FUNCTION STATEMACHINE


Author: atif (Guest)
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Hi,
I am trying to design state machine for bitslip function. But the 
simulation doesn't work correctly. Can any one please have a look and 
check where is the bug? I have tried a lot but cannot find where the bug 
is because according to my simulation, signal bitslip done should go 
down at the input data 17c?
please see the verilog code in attachement.

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