module top_tb();

reg clk 50,reset,test;

reg [2:0] A;

wire [6:0] switch;
wire lcd_on,lcd_rs,lcd_rw,lcd_en,lcd_4,lcd_4,lcd_5,lcd_6,lcd_7;

wire clk;
wire [15:0] out1,out2, out3,out4, out5, out6, out7;
wire [15:0] in1, in2, in3, in4, in5,in6, in7;
wire [6:0] AmpOut;

dummyinput u1 (.clk50(clk50), .test(test), .in1(in1), .in2(in2), 
.in3(in3), .in4(in4), .in5(in5),.in6(in6), .in7(in7),.clk(clk));

sort u2 (.clk(clk),.in1(in1), .in2(in2), .in3(in3), .in4(in4), 
.in5(in5), .in6(in6), .in7(in7), .out1(out1), .out2(out2), .out3(out3), 
.out4(out4), .out5(out5), .out6(out6), .out7(out7));

ampout u3 (.clk(clk),.reset(reset), .out1(out1), .out2(out2), 
.out3(out3), .out4(out4), .out5(out5), .out6(out6), .out7(out7), .A(A), 
.AmpOut(AmpOut), .switch(switch));

lcd u4 (.clk50(clk50), .AmpOut(AmpOut), .lcd_on(lcd_on), 
.lcd_rs(lcd_rs), .lcd_rw(lcd_rw), .lcd_en(lcd_en), .lcd_4(lcd_4), 
.lcd_5(lcd_5), .lcd_6(lcd_6), .lcd_7(lcd_7));

endmodule

can someone do the testbench for this?