# Forum: FPGA, VHDL & Verilog 4 bit ALU variable name question

 Author: Andrew M. (amiotto11) Posted on: 2019-02-21 05:28

Rate this post
 0 ▲ useful ▼ not useful
Im writing code for a 4bit Arithmetic Logic Unit in Verilog HDL as a
structural model. I need help programming the function for adding
alu_in_a+alu_in_b+Cin. I also need help with variable names. In this
project the ALU module is intended to have inputs alu_in_a and alu_in_b.
I designed all of my adders using A and B as inputs. I realized I don't
fully understand how module instantiation inside another module works,
and how inputs to one module are passed to another module for some
desired operation. I would very much appreciate clarification on this in
general and in the specific instance of the 4bit ALU. On a side note
this code does compile, but I suspect there are errors resulting from my
ignorance which will cause it to malfunction in simulation. Thanks!

// ALU

module ALU (input [3:0] alu_in_a, alu_in_b, OPCODE, input Cin, output
reg [3:0] Sum, output reg Cout, output OF);

reg [3:0] Bin;
wire [3:0] Bn, S;
wire Co;
com2s C1 (aluin_b, Bn);
ripple_adder_4bit FA4 (A, Bin, Cin, S, Co, OF);
always @ (*) begin
Bin = 4'b000; Sum = 4'b0000; Cout = 'b0;
case (OPCODE)

//ALU operations

// A+B : add
4'b1000 : begin
Bin = alu_in_b; Sum = S; Cout = Co;
end

// A+B+Cin : add with Cin
4'b1001 : begin
Bin = alu_in_b; Sum = S; Cout = Co; ***HELP***
end

// A-B : sub a from b
4'b1010 : begin
Bin = Bn; Sum = S; Cout = Co;
end

// ~(A&B) : bitwise NAND
4'b0000 : begin
Sum = ~alu_in_a&~alu_in_b;
end

// ~(A|B) : bitwise NOR
4'b0001 : begin
Sum = ~alu_in_a|~alu_in_b;
end

// A^B : bitwise XOR
4'b0010 : begin
Sum = alu_in_a^alu_in_b;
end

// ~A : bitwise inversion
4'b0100 : begin
Sum = ~alu_in_a;
end

// A_leftshift
4'b0101 : begin
Sum = alu_in_a << 1;
end
endcase
end
endmodule

// 4 Bit Ripple Carry Adder

module ripple_adder_4bit(input Cin, input [3:0] A, B, output [3:0] Sum,
output Cout, OF);

full_adder FA1(Sum, Cout1, A, B, Cin);
full_adder FA2(Sum, Cout2, A, B, Cout1);
full_adder FA3(Sum, Cout3, A, B, Cout2);
full_adder FA4(Sum, Cout, A, B, Cout3);
xor X1 (OF, Cout3, Cout);

endmodule

// Twos Compliment

module com2s (input [3:0] B, output [3:0] Bn);
wire [3:0] Bn1;
wire OF;
assign Bn1 = ~B;
ripple_adder_4bit FA4 (Bn1, 4'b0000, 1'b1, Bn, Cout, OF);

endmodule

module full_adder(output S, Cout, input A, B, Cin);
wire Sum1, Cout1, Cout2;
half_adder HA1(Sum1, Cout1, A, B);
half_adder HA2(Sum1, C, Sum, C);
or O1(Cout, Cout1, Cout2);

endmodule

module half_adder(output Sum, Cout, input A,B);
assign Sum = A^B;
assign Cout = A&B;

endmodule

 Author: Hallo (Guest) Posted on: 2019-02-23 08:59

Rate this post
 0 ▲ useful ▼ not useful
You should add the port name upfront:

 ripple_adder_4bit FA4 (.A(A), .Bin(Bin), .Cin(Cin), .S(S), .Co(Co), .OF(OF));

Otherwise you need to keep the port order as it defined in the module
and that might change...

You can also define localparam for your opcodes

### Rules — please read before posting

• Post long source code as attachment, not in the text
• $formula (LaTeX syntax)$