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VHDL output signal in hexadecimal instead of binary
von Guest (Guest)

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Hello.

I am trying to simulate a vhdl Code using a text files. the Output 
Signal is correct except that it's in binary. I would like to know what 
command line I can add to have it in hexadecimal. My Code look like 
this.

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file_open(vectors, "input_vectors.txt", read_mode);

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file_open(results, "output_results.txt", write_mode);

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while not endfile(vectors) loop

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   readline(vectors, iline);

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   read(iline, a_in);

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   ...

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   write(oline, output_data); -- it's any modification needed here 

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end loop;

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file_close(vectors);

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file_close(results);


Many thanks

  


  



  

  
:
    Edited by Moderator
  

  


  

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    Re: VHDL output signal in hexadecimal instead of binary
  


  

    

      von
      
        Duke Scarring (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Maybe you find some hints here:
https://stackoverflow.com/questions/37879954/how-to-write-an-integer-to-stdout-as-hexadecimal-in-vhdl

  


  




  

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    Re: VHDL output signal in hexadecimal instead of binary
  


  

    

      von
      
        Guest (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Hello.

@moderator thanks for the edit.

Thanks a lot for the link Duke. I have tried one of the example and it 
work. I just have to Change the "write" line to

 hwrite (oline, output_data);

Once again thanks for the help

  


  




  

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    Re: VHDL output signal in hexadecimal instead of binary
  


  

    

      von
      
        Guest (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Hallo again.

I don't know if I should start a new tread or continue here. I am facing 
another Problem. I would like the values I am reading from the input 
text file to appear on the waveform window of the Simulation Software 
(Active-HDL). These Signals only appear as Zero (0) in the waveform. My 
Code look like:


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 Signal e_in            : std_logic;

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       Signal a_in            : std_logic_vector(31 downto 0);

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       Signal b_in            : std_logic_vector(3 downto 0);

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      ...

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      process

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          variable s         : string(1 to 300);

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          variable iline     : line;

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          variable oline     : line;

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          variable e_in      : std_logic;

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          variable a_in      : std_logic_vector (31 downto 0);

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          variable sapce     : character;

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          ...

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          file_open(vectors, "input_vectors.txt", read_mode);

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          file_open(results, "output_results.txt", write_mode);

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         while not endfile(vectors) loop

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             readline(vectors, iline);

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             if (s(1 to 3)= "#AE") then

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             read(iline, space);

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             hread(iline, a_in);  --This value to appear on the waveform

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             read (iline, space);

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             read (iline, e_in);  -- as well as this value

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             read (iline, space);

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             read (iline, b_in);  -- and this one too

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             in_a <= a_in;

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             in_e <= e_in;

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             in_b <= b_in;

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           elsif

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              ...

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             hwrite(oline, output_data);

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             end loop;

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            file_close(vectors);

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            file_close(results);


the Content of my Input file

1
#AE 0000001A 1 0010 

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      #CDE 00FC0011 0001 00000274

3
      ...


Many thanks

  


  




  

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