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Forum: FPGA, VHDL & Verilog Rising and falling edges


Author: Bob T. (mhzdriver)
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I have some simple VHDL code that starts from a rising edge of a clock. 
At every nth clock cycle or so, something happens. Is there a way to get 
an action on the falling edge, effectively doubling the frequency?
In the example below, I would like for a response to occur at the next 
falling edge after the rising edge of the 10th clock edge. Is there a 
simple way to do this and how would I go about doing that?


if rising_edge(CLK) then --            clk_cntr <= clk_cntr + 1;

if clk_cntr = (10) then
  PIN(5) <='1';

end if;

if clk_cntr = (11) then
  PIN(5) <='0';

end if;

if clk_cntr > (11) then
  clk_cntr <= (others => '0');
end if;

end if;

Author: Bob T. (mhzdriver)
Posted on:

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i found a solution.

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