I have some simple VHDL code that starts from a rising edge of a clock.
At every nth clock cycle or so, something happens. Is there a way to get
an action on the falling edge, effectively doubling the frequency?
In the example below, I would like for a response to occur at the next
falling edge after the rising edge of the 10th clock edge. Is there a
simple way to do this and how would I go about doing that?
if rising_edge(CLK) then -- clk_cntr <= clk_cntr + 1;
if clk_cntr = (10) then
if clk_cntr = (11) then
if clk_cntr > (11) then
clk_cntr <= (others => '0');